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TBB1004DMTL-E Datasheet(PDF) 6 Page - Renesas Technology Corp |
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TBB1004DMTL-E Datasheet(HTML) 6 Page - Renesas Technology Corp |
6 / 10 page TBB1004 Rev.11.00 Aug 22, 2006 page 6 of 9 400 300 200 100 0 50 100 150 200 0 12 3 4 5 25 20 15 10 5 VG2S = 4 V VG1 = VDS 25 20 15 10 5 0 1 234 5 50 40 30 20 10 0 12 34 5 VDS = 5 V RG = 100 kΩ VDS = 5 V Ambient Temperature Ta ( °C) Maximum Channel Power Dissipation Curve Typical Output Characteristics (FET1) Drain to Source Voltage VDS (V) Drain Current vs. Gate1 Voltage (FET1) Gate1 Voltage VG1 (V) 2 V VG2S = 1 V 4 V 3 V * Value on the glass epoxy board (49mm × 38mm × 1mm) 120 kΩ 150 kΩ 180 kΩ Gate1 Voltage VG1 (V) Forward Transfer Admittance vs. Gate1 Voltage (FET1) VG2S = 4 V 150 k Ω RG = 68 kΩ 100 k Ω 0 1 2 3 4 4 3 2 1 0 Gate2 to Source Voltage VG2S (V) Input Capacitance vs. Gate2 to Source Voltage (FET1) 30 25 20 15 10 5 0 10 20 50 100 200 500 1000 VDS = 5 V VG1 = 5 V VG2S = 4 V Drain Current vs. Gate Resistance (FET1) Gate Resistance RG (kΩ) VDS = 5 V VG1 = 5 V RG = 100 kΩ f = 1 MHz |
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