M66288FP

REJ03F0156-0310 Rev.3.10 Apr.04.2008

Page 8 of 23

Mode4 Operation Description

<Mode 4>

In mode 4, two pieces of 256K-word x 12-bit FIFO can be controlled completely

independently. Taking FIFO (A) as an example, the operation of FIFO memory is

described below. The operation of FIFO (B) is the same as that of FIFO (A).

When write enable input WEA is "L", the contents of data input DA<7:0> and

DB<3:0> are written into FIFO (A) in synchronization with the rising of write clock

input WCKA. At this time, the write address counter of FIFO (A) is incremented.

When WEA is "H", this IC disable to write data into FIFO(A) and the write address

counter of FIFO (A) is not incremented.

When write reset input WRESA is "L", the write address counter of FIFO (A) is

initialized.

When read enable input REA is "L", the contents of FIFO (A) are outputted to data

output QA<7:0> and QB<3:0> in synchronization with the rising of read clock

input RCKA. At this time, the read address counter of FIFO (A) is incremented.

When REA is "H", this IC disable to read data from FIFO (A) and the read address

counter of FIFO (A) is not incremented. Also QA<7:0> and QB<3:0> become high

impedance state.

When read reset input RRESA is "L", the read address counter of FIFO (A) is

initialized.

Also, set the 12-bit I/O buses of FIFO (A) and FIFO (B) as shown in the table

below. In mode 4, only all pins for the A/B-system, DC<7:0> and QC<7:0> are

used. Therefore the write/read control pins for the C-system should be fixed at "L"

or "H".

External pin

name

Data input

bus of FIFO

(A)

External pin

name

Data output

bus of FIFO

(A)

External pin

name

Data input

bus of FIFO

(B)

External pin

Name

Data output

bus of FIFO

(B)

DA<7>

11

QA<7>

11

DC<7>

11

QC<7>

11

DA<6>

10

QA<6>

10

DC<6>

10

QC<6>

10

DA<5>

9

QA<5>

9

DC<5>

9

QC<5>

9

DA<4>

8

QA<4>

8

DC<4>

8

QC<4>

8

DA<3>

7

QA<3>

7

DC<3>

7

QC<3>

7

DA<2>

6

QA<2>

6

DC<2>

6

QC<2>

6

DA<1>

5

QA<1>

5

DC<1>

5

QC<1>

5

DA<0>

4

QA<0>

4

DC<0>

4

QC<0>

4

DB<3>

3

QB<3>

3

DB<7>

3

QB<7>

3

DB<2>

2

QB<2>

2

DB<6>

2

QB<6>

2

DB<1>

1

QB<1>

1

DB<5>

1

QB<5>

1

DB<0>

0

QB<0>

0

DB<4>

0

QB<4>

0

DA<7:0>

WCKA

WRESA

WEA

12

12

256K-w

x

12-bit

FIFO(A)

QA<7:0>

DB<3:0>

QB<3:0>

256K-w

x

12-bit

FIFO(B)

12

12

QC<7:0>

DB<7:4>

QB<7:4>

WCKB

WRESB

WEB

DC<7:0>

RCKB

RRESB

REB

RCKA

RRESA

REA