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M37512FCH-XXXHP Datasheet(PDF) 8 Page - Renesas Technology Corp |
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M37512FCH-XXXHP Datasheet(HTML) 8 Page - Renesas Technology Corp |
8 / 87 page Feb 18, 2005 page 8 of 85 REJ03B0122-0101 7512 Group Fig. 6 Structure of CPU mode register CPU mode register (CPUM : address 003B16) b7 b0 Note : All bits in this register are protected by protect mode. Processor mode bits b1 b0 0 0 : Single-chip mode 01 : 1 0 : Not available 11 : Stack page selection bit 0 : 0 page 1 : 1 page Clock source switch bit 0 : Built-in high speed oscillating function 1: XCIN–XCOUT oscillation function Port XC switch bit 0 : I/O port function (stop oscillation) 1: XCIN–XCOUT oscillation function Main clock (XIN–XOUT) stop bit 0 : Oscillation 1 : Stopped Main clock division ratio selection bits b7 b6 00 : φ = f(XIN)/2 (high-speed mode) 01 : φ = f(XIN)/8 (middle-speed mode) 10 : φ = f(XIN)/2 (low-speed mode) 1 1 : Not available [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit, etc. The CPU mode register is allocated at address 003B16. |
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