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M66290AFP Datasheet(PDF) 11 Page - Renesas Technology Corp |
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M66290AFP Datasheet(HTML) 11 Page - Renesas Technology Corp |
11 / 54 page USB DEVICE CONTROLLER M66290AGP/FP MITSUBISHI <DIGITAL ASSP> 10 (2) Interrupts There are eight f actors of interrupt to CPU. When interrupt occurred, the f actor can be known to ref er to "Interrupt Status Register 0" and "Interrupt Status Register 1". These interrupts can be set of its enable/disable independently to set "Interrupt Enable Register 0" and "Interrupt Enable Register 1". If disable is set, interrupt is not occurred but interrupt status f lag is set. Each f actor of interrupt is shown in the table below, and also describes below the interrupt conditions and how to deal with the interrupt. VBUS Vbus interrupt (connec/shut-down detect) Status bit Name Change of the Vbus input (both "L" to "H" and "H" to "L") Vbus RESM Resume detect interrupt Abstract of interrupt f actor Resume signal receiv ed in suspended SOFR SOF detect interrupt Receiv ed SOF DVST dev ice state transition interrupt Shif t of dev ice state DVSQ[2:0] CTRT Control transf er stage transition interrupt Stage shif t of control transf er CTSQ[2:0] BEMP Endpoint buff er empty /size-ov er interrupt In each endpoint, when data transmit of all buff er is ended and buff er is empty , or in OUT transf er, receiv ed packet which exceeds max packet size. EPB_EMP_OVR[5:0] INTN Endpoint buff er not ready interrupt When buff er is in not ready state (SIE cannot read and write) to IN/OUT token of each endpoint. EPB_NRDY [5:0] INTR Endpoint buff er ready interrupt When buff er of each endpoint became ready (read enable/write enable) EPB_RDY [5:0] Relational status bit Vbus (connect/shut down) interrupt (VBUS) Interrupt occurs when Vbus input state is changed (both "L" to "H" and "H" to "L"). To know Vbus input state, conf irm the Vbus bit of interrupt status register 0. Conf irmation of Vbus bit must be done af ter enabled internal clock operation. This interrupt can be occurred ev en if the internal clock(sck) is halted. To clear the status f lag, enables the internal clock(sck) in operation and then write "0". If the internal clock(sck) is halted, status f lag can not be cleared. This interrupt is usef ul to detect connect/shut-down of USB f or prepareration/close of USB transf ers. Summary of interrupts Resume detect interrupt (RESM) If dev ice state is in suspended state and resume interrupt enable f lag is set, interrupt occurs when USB bus state is changed ("J" to "K" or "SE0"). This interrupt can be occurred ev en if the internal clock(sck) is halted. To clear the status f lag, set the internal clock(sck) in operation and then write "0". If the internal clock(sck) is halted, status f lag can not be cleared. SOF detect interrupt (SOFR) Interrupt occurs when detect SOF. Device state transition interrupt (DVST) M66290A manages the dev ice state by H/W. It manages Powered, Def ault, Address, Conf igured, and Suspended state. Dev ice state can be known to ref er to "Interrupt Status Register 0". As to dev ice state shif t, see the item of "Dev ice state shif t" in "(3) Control transf er/emulation" in the latter part. Dev ice state transition interrupt occurs when dev ice state shif ted. The number of f actors is f our, that is, USB bus reset detect, suspend detect, execution of "Set Address", and execution of "Set Conf iguration". USB reset is detected when SE0 state ov er 2.5us is continued on D+, D- terminal. Suspend is detected when idle state ov er 3ms is continued on D+, D- terminal. |
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