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M66596WG Datasheet(PDF) 10 Page - Renesas Technology Corp |
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M66596WG Datasheet(HTML) 10 Page - Renesas Technology Corp |
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10 / 131 page  M66596FP/WG rev .1.00 2006.3.14 page 10 of 127 1.7 An overview of functions 1.7.1 The function selection The controller can change a host function and a peripheral function by register setup. When which of the Host function and the Peripheral function is chosen, hardware recognizes Hi-Speed or Full-Speed automatically. 1.7.2 Bus interfaces The controller supports the bus interfaces noted below. 1.7.2.1 External bus interface The controller uses a CPU bus interface to access control registers. The bus interface with the CPU supports the two access methods noted below. The Chip Select pin (CS_N) and the three strobe pins (RD_N, WR0_N and WR1_N) should be used for access. (1) (16-bit separate bus The six address buses (A6-1) and the 16 data buses (D15-0) are used. (2) 16-bit multiplex bus The ALE pin (ALE) and the 16 data buses (D15-0) are used. The data buses are used for addresses and data on a time-shared basis. The separate bus and multiplex bus are selected based on the MPBUS pin signal level when the H/W reset is canceled. 1.7.2.2 Accessing the buffer memory The controller supports the two methods described below to access the USB data transfer buffer memory. (1) CPU access Addresses and control signals should be used to write data to the buffer memory or read it from the buffer memory. (2) DMA access Data should be written to the buffer memory of the controller, or read from the buffer memory, from the DMAC in the CPU or a dedicated DMAC. USB data communication is done using Little Endian. There is a byte Endian swap function for FIFO port access, and when using 16-bit access, the Endian can be switched using the register settings. 1.7.2.3 DMA access methods When using DMA access to access the buffer memory, the two access methods noted below can be selected. (1) Method using a bus shared with the CPU (2) Method using a dedicated bus (split bus) 1.7.3 USB events The controller notifies the user’s system of USB operation events by means of interrupts. Moreover, with a pipe for which the DMA interface has been selected, the system is notified that the buffer memory of the controller can be accessed by asserting the DREQ signal. There are 12 types of interrupts and 39 causes for interrupts being generated. The user can select whether or not interrupt notification is permitted for each type and each cause, using settings in the control program for the user system. |
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