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M38034F2L-XXXWG Datasheet(PDF) 9 Page - Renesas Technology Corp |
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M38034F2L-XXXWG Datasheet(HTML) 9 Page - Renesas Technology Corp |
9 / 119 page Rev.1.01 Jan 25, 2008 Page 9 of 117 REJ03B0212-0101 3803 Group (Spec.L) FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 3803 group (Spec.L) uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as data transfer, etc. are executed mainly through the accumulator. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Index Register Y (Y)] The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. [Stack Pointer (S)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is “0”, the high-order 8 bits becomes “0016”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”. The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 8. Store registers other than those described in Figure 7 with program when the user needs them during interrupts or subroutine calls (see Table 4). [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed. Fig 7. 740 Family CPU register structure Processor Status Register (PS) Carry Flag Zero Flag Interrupt Disable Flag Decimal Mode Flag Break Flag Index X Mode Flag Overflow Flag Negative Flag b7 b0 b15 Program Counter Stack Pointer Index Register Y Index Register X Accumulator A X Y S PCL PCH C Z I D B T V N b7 b0 b7 b0 b7 b0 b7 b0 b7 b0 |
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