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M64895BGP Datasheet(PDF) 2 Page - Renesas Technology Corp |
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M64895BGP Datasheet(HTML) 2 Page - Renesas Technology Corp |
2 / 12 page M64895BGP Rev.1.0, Aug.27 2003, page 2 of 11 Pin Configuration (TOP VIEW) 1 1 2 3 4 5 6 7 8 16 9 10 11 12 13 14 15 OUTLINE 16P2Z PRESCALER INPUT fin GND GND SUPPLY VOLTAGE 2 Vcc2 SUPPLY VOLTAGE 1 Vcc1 BAND SWITCHING OUTPUTS BS4 BS3 BS2 BS1 Xin ADS CHIP ADDRESS INPUT SDA DATAINPUT SCL CLOCK INPUT LD Lock OUTPUT Vcc3 SUPPLY VOLTAGE 3 Vtu TUNING OUTPUT Vin FILTER INPUT CRYSTAL OSCILLATOR Pin Description Symbol Pin No. Pin name Function fin 1 Prescaler input Input for the VCO frequency. GND 2 GND Ground to 0 V Vcc1 3 Power supply voltage 1 Power supply voltage terminal. 5.0 V+/–0.5 V Vcc2 4 Power supply voltage 2 Power supply for band switching. Vcc1 to 13.2 V BS4 BS3 BS2 BS1 5 6 7 8 Band switching outputs PNP open collector method is used. When the band switching data is “H”, the output is “ON”. When it is “L”, the output is “OFF”. Vin 9 Filter input (Charge pump output) This is the output terminal for the LPF input and charge pump output. When the phase of the programmable divider output (f1/N) is ahead compared to the reference frequency (fref), the “source” current state becomes active. If it is lag, the “sink” current becomes active. If the phases are the same, the high impedance state becomes active. Vtu 10 Tuning output This supplies the tuning voltage. Vcc3 11 Power supply voltage 3 Power supply voltage for tuning voltage 28 to 35 V LD/ftest 12 Lock detect/Test port Lock detector is output. Programmable freq. Divider output and reference freq. output is selected by the test mode. SCL 13 Clock input Data is read into the shift register when the clock signal falls. SDA 14 Data input Input for band SW and programmable frequency. divider set falls. ADS 15 Address switching input Chip address sets it up with the input condition of terminal. X in 16 This is connected to theCrystal oscillator. 4.0 MHz crystal oscillator connected. |
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