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M66515FP Datasheet(PDF) 4 Page - Renesas Technology Corp

Part # M66515FP
Description  Laser Diode Driver/Controller
Download  12 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M66515FP Datasheet(HTML) 4 Page - Renesas Technology Corp

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M66515FP
Rev.1.00, Sep.22.2003, page 4 of 11
5. RO pin
The RO pin is connected to the laser driving current load resistance; current essentially equal to ISW flows from this pin.
The load resistance is connected between this pin and VCC; by this means the Power dissipation within the IC is
reduced.
However, the circuit operation requires that the voltage at this pin be 2.5 V or above. Hence if the maximum value of
ISW is ISW(max), then the maximum value RO(max) of the load resistance RO is as follows.
For example, if VCC(min)=4.75 V and ISW(max)=120 mA, then RO(max)=18.8
Ω. In other words, when setting the
resistance RS such that the maximum value of ISW is 120 mA, RO should be 18.8
Ω or lower.
6. Sample-and-hold circuit
(1) Summary of circuit operation
The following is a summary of operation of the sample hold circuit within the M66515.
A PD current arising upon LD light emission flows through the resistance connected between 1RM and 2RM, giving
rise to a potential difference (VM). This VM is compared with the voltage applied to the pin Vr, and if VM<Vr, pin CH is
a constant current source which charges the external capacitor. If VM>Vr, pin CH is a constant current sink which
discharges the external capacitor. This operation is performed when the
S /H input is "L" (sample); when the S/H input
is "H", the CH pin is kept in the high-impedance state (hold), regardless of VM, Vr, and the DATA input state.
Function table
Input
Switched state
ENB
S/H
Vm, Vr
SW1
SW2
Tr1
Output
H
X
X
OFF
OFF
ON
Fixed at "L"
L
H
X
OFF
OFF
OFF
High-impedance state (hold)
LL
VM < Vr
ON
OFF
OFF
Constant current source (sample)
VM > Vr
OFF
ON
OFF
Constant current sink (sample)
X: arbitrary
(2) APC operation timing chart
An example of an APC operation timing chart for a given sample hold control signal is shown below.
In this example, a case is shown in which it is assumed that the direction of the leakage current of the CH pin in the hold
state is the direction flowing out from the M66515 (the negative direction).


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