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HD6432646 Datasheet(PDF) 11 Page - Renesas Technology Corp |
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HD6432646 Datasheet(HTML) 11 Page - Renesas Technology Corp |
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11 / 1165 page  Rev. 5.00 Sep 22, 2005 page xi of xxvi 4.7 Notes on Use of the Stack................................................................................................. 97 Section 5 Interrupt Controller .......................................................................................... 99 5.1 Overview .......................................................................................................................... 99 5.1.1 Features................................................................................................................ 99 5.1.2 Block Diagram..................................................................................................... 100 5.1.3 Pin Configuration ................................................................................................ 101 5.1.4 Register Configuration......................................................................................... 101 5.2 Register Descriptions........................................................................................................102 5.2.1 System Control Register (SYSCR)...................................................................... 102 5.2.2 Interrupt Priority Registers A to H, J, K, M (IPRA to IPRH, IPRJ, IPRK, IPRM)................................................................... 103 5.2.3 IRQ Enable Register (IER) .................................................................................. 104 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 105 5.2.5 IRQ Status Register (ISR) ................................................................................... 106 5.3 Interrupt Sources............................................................................................................... 107 5.3.1 External Interrupts ............................................................................................... 107 5.3.2 Internal Interrupts ................................................................................................ 109 5.3.3 Interrupt Exception Handling Vector Table ........................................................ 109 5.4 Interrupt Operation ........................................................................................................... 113 5.4.1 Interrupt Control Modes and Interrupt Operation................................................ 113 5.4.2 Interrupt Control Mode 0..................................................................................... 116 5.4.3 Interrupt Control Mode 2..................................................................................... 118 5.4.4 Interrupt Exception Handling Sequence .............................................................. 120 5.4.5 Interrupt Response Times .................................................................................... 121 5.5 Usage Notes ...................................................................................................................... 122 5.5.1 Contention between Interrupt Generation and Disabling..................................... 122 5.5.2 Instructions that Disable Interrupts...................................................................... 123 5.5.3 Times when Interrupts are Disabled .................................................................... 123 5.5.4 Interrupts during Execution of EEPMOV Instruction ......................................... 124 5.5.5 IRQ Interrupts...................................................................................................... 124 5.6 DTC Activation by Interrupt............................................................................................. 124 5.6.1 Overview ............................................................................................................. 124 5.6.2 Block Diagram..................................................................................................... 125 5.6.3 Operation ............................................................................................................. 125 Section 6 PC Break Controller (PBC)........................................................................... 127 6.1 Overview .......................................................................................................................... 127 6.1.1 Features................................................................................................................ 127 6.1.2 Block Diagram..................................................................................................... 128 6.1.3 Register Configuration......................................................................................... 129 |
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