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ADS62P24 Datasheet(PDF) 5 Page - Texas Instruments

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Part # ADS62P24
Description  DUAL CHANNEL, 12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ADS62P24 Datasheet(HTML) 5 Page - Texas Instruments

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ELECTRICAL CHARACTERISTICS
ADS62P25, ADS62P24
ADS62P23, ADS62P22
SLAS576A – OCTOBER 2007 – REVISED FEBRUARY 2008
Typical values are at 25
°C, AVDD = 3.3 V, DRVDD = 1.8 V to 3.3 V, maximum rated sampling frequency, 50% clock duty
cycle, –1 dBFS differential analog input, internal reference mode, applies to CMOS and LVDS interfaces, unless otherwise
noted.
Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, DRVDD = 3.3 V,
unless otherwise noted.
ADS62P25
ADS62P24
ADS62P23
ADS62P22
FS = 125 MSPS
FS = 105 MSPS
FS = 80 MSPS
FS = 65 MSPS
PARAMETER
UNIT
MIN
TYP
MA
MIN
TYP
MA
MIN
TYP
MA
MIN
TYP
MA
X
X
X
X
RESOLUTION
12
12
12
12
Bits
ANALOG INPUT
Differential input voltage range
2
2
2
2
VPP
Differential input resistance (dc)
> 1
> 1
> 1
> 1
M
see Figure 82
Differential input capacitance
7
7
7
7
pF
see Figure 83
Analog input bandwidth
450
450
450
450
MHz
Analog input common mode current (per input pin
1.3
1.3
1.3
1.3
µA/MSPS
of each ADC)
REFERENCE VOLTAGES
VREFB
Internal reference bottom voltage
1
1
1
1
V
VREFT
Internal reference top voltage
2
2
2
2
V
VCM
Common mode output voltage
1.5
1.5
1.5
1.5
V
VCM output current capability
4
4
4
4
mA
DC ACCURACY
No missing codes
Specified
Specified
Specified
Specified
EO
Offset error
-10
± 2
10
-10
± 2
10
-10
± 2
10
-10
± 2
10
mV
Offset error temperature coefficient
0.05
0.05
0.05
0.05
mV/
°C
There are two sources of gain error – internal reference inaccuracy and channel gain error
Gain error due to internal reference inaccuracy
±0.2
EGREF
-2
±0.25
2
-2
2
-2
±0.25
2
-2
±0.25
2
% FS
alone, (
ΔVREF /2) %
5
EGCHAN
Gain error of channel alone(1)
-1
±0.3
1
-1
±0.3
1
-1
±0.3
1
-1
±0.3
1
% FS
across devices & across channels within a device
0.00
Channel gain error temperature coefficient
0.005
0.005
0.005
Δ%/
°C
5
-0.75
±0.3
-
±0.3
-
±0.3
-
±0.3
DNL
Differential nonlinearity
LSB
0.75
0.75
0.75
INL
Integral nonlinearity
-2
±0.6
2
-2
±0.6
2
-2
±0.6
2
-2
±0.6
2
LSB
POWER SUPPLY
IAVDD
Analog supply current
240
275
212
240
177
200
153
175
mA
No external load
Digital supply current,
15
13
11.5
10
mA
capacitance
CMOS interface
IDRVDD
DRVDD = 1.8 V
10 pF external
28
25
21
18
mA
FIN= 2 MHZ
(2)
load capacitance
Digital supply current, LVDS interface
IDRVDD
DRVDD = 3.3 V
73
73
73
73
mA
with 100
Ω external termination
PAVDD
Analog power dissipation
799
908
710
792
594
660
515
578
mW
No external load
27
24
21
18
mW
Digital power dissipation
capacitance
PDRVDD
CMOS interface
10 pF external
DRVDD = 1.8 V (3)
51
45
38
32
mW
load capacitance
Global powerdown
50
75
50
75
50
75
50
75
mW
(1)
This is specified by design and characterization; it is not tested in production.
(2)
In CMOS mode, the DRVDD current scales with the sampling frequency, load capacitance on output pins, input frequency and supply
voltage (see Figure 79 and CMOS power dissipation in the application section).
(3)
The maximum DRVDD current depends on the actual load capacitance on the digital output lines. Note that the maximum
recommended load capacitance is 10 pF.
Copyright © 2007–2008, Texas Instruments Incorporated
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Product Folder Link(s): ADS62P25, ADS62P24 ADS62P23, ADS62P22


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