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R5F3651KNFC Datasheet(PDF) 10 Page - Renesas Technology Corp |
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R5F3651KNFC Datasheet(HTML) 10 Page - Renesas Technology Corp |
10 / 829 page A - 3 7.2 Registers ........................................................................................................... 77 7.2.1 Voltage Detection 2 Circuit Flag Register (VCR1)...................................... 78 7.2.2 Voltage Detection Circuit Operation Enable Register (VCR2).................... 79 7.2.3 Voltage Monitor Function Select Register (VWCE) .................................... 80 7.2.4 Voltage Detection 1 Level Select Register (VD1LS)................................... 80 7.2.5 Voltage Monitor 0 Circuit Control Register (VW0C).................................... 82 7.2.6 Voltage Monitor 1 Circuit Control Register (VW1C).................................... 83 7.2.7 Voltage Monitor 2 Circuit Control Register (VW2C).................................... 85 7.3 Optional Function Select Area........................................................................... 87 7.3.1 Optional Function Select Address (OFS1) ................................................. 87 7.4 Operations......................................................................................................... 88 7.4.1 Digital Filter................................................................................................. 88 7.4.2 Voltage Detection 0 Circuit ......................................................................... 89 7.4.3 Voltage Detection 1 Circuit ......................................................................... 91 7.4.4 Voltage Detection 2 Circuit ......................................................................... 94 7.5 Interrupts ........................................................................................................... 97 8. Clock Generator ..................................................................................... 98 8.1 Introduction........................................................................................................ 98 8.2 Registers ......................................................................................................... 101 8.2.1 Processor Mode Register 0 (PM0) ........................................................... 102 8.2.2 System Clock Control Register 0 (CM0)................................................... 103 8.2.3 System Clock Control Register 1 (CM1)................................................... 105 8.2.4 Oscillation Stop Detection Register (CM2) ............................................... 107 8.2.5 Peripheral Clock Select Register (PCLKR) .............................................. 109 8.2.6 PLL Control Register 0 (PLC0)................................................................. 110 8.2.7 Processor Mode Register 2 (PM2) ............................................................111 8.2.8 40 MHz On-Chip Oscillator Control Register 0 (FRA0) ............................ 112 8.3 Clocks Generated by Clock Generators.......................................................... 113 8.3.1 Main Clock................................................................................................ 113 8.3.2 PLL Clock ................................................................................................. 115 8.3.3 fOCO40M ................................................................................................. 116 8.3.4 fOCO-F ..................................................................................................... 116 8.3.5 125 kHz On-Chip Oscillator Clock (fOCO-S)............................................ 117 8.3.6 Sub Clock (fC) .......................................................................................... 118 |
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