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HD6433024TE Datasheet(PDF) 11 Page - Renesas Technology Corp |
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HD6433024TE Datasheet(HTML) 11 Page - Renesas Technology Corp |
11 / 841 page Rev. 2.00 Sep 20, 2005 page xi of xxxviii Section 5 Interrupt Controller .......................................................................................... 83 5.1 Overview........................................................................................................................... 83 5.1.1 Features................................................................................................................ 83 5.1.2 Block Diagram..................................................................................................... 84 5.1.3 Pin Configuration ................................................................................................ 85 5.1.4 Register Configuration......................................................................................... 85 5.2 Register Descriptions........................................................................................................85 5.2.1 System Control Register (SYSCR) ...................................................................... 85 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)............................................. 86 5.2.3 IRQ Status Register (ISR).................................................................................... 92 5.2.4 IRQ Enable Register (IER) .................................................................................. 93 5.2.5 IRQ Sense Control Register (ISCR) .................................................................... 94 5.3 Interrupt Sources............................................................................................................... 95 5.3.1 External Interrupts ............................................................................................... 95 5.3.2 Internal Interrupts ................................................................................................ 96 5.3.3 Interrupt Exception Handling Vector Table......................................................... 96 5.4 Interrupt Operation ........................................................................................................... 100 5.4.1 Interrupt Handling Process .................................................................................. 100 5.4.2 Interrupt Exception Handling Sequence .............................................................. 105 5.4.3 Interrupt Response Time...................................................................................... 106 5.5 Usage Notes ...................................................................................................................... 107 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction...................... 107 5.5.2 Instructions that Inhibit Interrupts ....................................................................... 108 5.5.3 Interrupts during EEPMOV Instruction Execution.............................................. 108 Section 6 Bus Controller ................................................................................................... 109 6.1 Overview........................................................................................................................... 109 6.1.1 Features................................................................................................................ 109 6.1.2 Block Diagram..................................................................................................... 110 6.1.3 Pin Configuration ................................................................................................ 111 6.1.4 Register Configuration......................................................................................... 112 6.2 Register Descriptions........................................................................................................ 112 6.2.1 Bus Width Control Register (ABWCR)............................................................... 112 6.2.2 Access State Control Register (ASTCR) ............................................................. 113 6.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 114 6.2.4 Bus Release Control Register (BRCR) ................................................................ 118 6.2.5 Bus Control Register (BCR) ................................................................................ 120 6.2.6 Chip Select Control Register (CSCR).................................................................. 122 6.2.7 Address Control Register (ADRCR) ................................................................... 123 6.3 Operation .......................................................................................................................... 124 6.3.1 Area Division....................................................................................................... 124 |
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