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M37540M2-XXXGP Datasheet(PDF) 11 Page - Renesas Technology Corp |
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M37540M2-XXXGP Datasheet(HTML) 11 Page - Renesas Technology Corp |
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11 / 366 page  vi List of figures 7540 Group Fig. 2.3.1 Memory map of registers relevant to timer 1 ........................................................ 2-36 Fig. 2.3.2 Structure of Prescaler 1 ............................................................................................ 2-36 Fig. 2.3.3 Structure of Timer 1 .................................................................................................. 2-37 Fig. 2.3.4 Structure of MISRG ................................................................................................... 2-37 Fig. 2.3.5 Structure of Interrupt request register 2 ................................................................. 2-38 Fig. 2.3.6 Structure of Interrupt control register 2 .................................................................. 2-38 Fig. 2.4.1 Memory map of registers relevant to timer X ........................................................ 2-40 Fig. 2.4.2 Structure of Port P0 direction register .................................................................... 2-41 Fig. 2.4.3 Structure of Port P1 direction register .................................................................... 2-41 Fig. 2.4.4 Structure of Timer X mode register ......................................................................... 2-42 Fig. 2.4.5 Structure of Prescaler X ............................................................................................ 2-43 Fig. 2.4.6 Structure of Timer X .................................................................................................. 2-43 Fig. 2.4.7 Structure of Timer count source set register ......................................................... 2-44 Fig. 2.4.8 Structure of Interrupt request register 1 ................................................................. 2-45 Fig. 2.4.9 Structure of Interrupt control register 1 .................................................................. 2-45 Fig. 2.4.10 Setting method for timer mode .............................................................................. 2-47 Fig. 2.4.11 Connection of timer and setting of division ratio ................................................ 2-48 Fig. 2.4.12 Example of control procedure ................................................................................ 2-49 Fig. 2.4.13 Setting method for pulse output mode (1) ........................................................... 2-50 Fig. 2.4.14 Setting method for pulse output mode (2) ........................................................... 2-51 Fig. 2.4.15 Example of peripheral circuit .................................................................................. 2-52 Fig. 2.4.16 Connection of timer and setting of division ratio ................................................ 2-52 Fig. 2.4.17 Example of control procedure ................................................................................ 2-53 Fig. 2.4.18 Setting method for event counter mode (1) ......................................................... 2-54 Fig. 2.4.19 Setting method for event counter mode (2) ......................................................... 2-55 Fig. 2.4.20 Example of peripheral circuit .................................................................................. 2-56 Fig. 2.4.21 Method of measuring water flow rate ................................................................... 2-56 Fig. 2.4.22 Example of control procedure ................................................................................ 2-57 Fig. 2.4.23 Setting method for pulse width measurement mode (1) .................................... 2-58 Fig. 2.4.24 Setting method for pulse width measurement mode (2) .................................... 2-59 Fig. 2.4.25 Connection of timer and setting of division ratio ................................................ 2-60 Fig. 2.4.26 Example of control procedure ................................................................................ 2-61 Fig. 2.5.1 Memory map of registers relevant to timer Y and timer Z .................................. 2-63 Fig. 2.5.2 Structure of Port P0 direction register .................................................................... 2-64 Fig. 2.5.3 Structure of Port P3 direction register .................................................................... 2-64 Fig. 2.5.4 Structure of Pull-up control register ........................................................................ 2-65 Fig. 2.5.5 Structure of Port P1P3 control register .................................................................. 2-65 Fig. 2.5.6 Structure of Timer Y, Z mode register .................................................................... 2-66 Fig. 2.5.7 Structure of Prescaler Y, Prescaler Z ..................................................................... 2-66 Fig. 2.5.8 Structure of Timer Y secondary, Timer Z secondary ........................................... 2-67 Fig. 2.5.9 Structure of Timer Y primary, Timer Z primary ..................................................... 2-67 Fig. 2.5.10 Structure of Timer Y, Z waveform output control register ................................. 2-68 Fig. 2.5.11 Structure of One-shot start register ....................................................................... 2-68 Fig. 2.5.12 Structure of Timer count source set register ....................................................... 2-69 Fig. 2.5.13 Structure of Interrupt edge selection register ...................................................... 2-69 Fig. 2.5.14 Structure of CPU mode register ............................................................................ 2-70 Fig. 2.5.15 Structure of Interrupt request register 1 ............................................................... 2-71 Fig. 2.5.16 Structure of Interrupt request register 2 ............................................................... 2-71 Fig. 2.5.17 Structure of Interrupt control register 1 ................................................................ 2-72 Fig. 2.5.18 Structure of Interrupt control register 2 ................................................................ 2-72 Fig. 2.5.19 Setting method for timer mode .............................................................................. 2-74 Fig. 2.5.20 Example of peripheral circuit .................................................................................. 2-75 |
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