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M38K07ME Datasheet(PDF) 8 Page - Renesas Technology Corp |
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M38K07ME Datasheet(HTML) 8 Page - Renesas Technology Corp |
8 / 328 page Rev.2.00 Oct 05, 2006 page 4 of 13 38K0 Group REJ09B0337-0200 List of figures CHAPTER 1 HARDWARE Fig. 1 Pin configuration of 38K0 group ........................................................................................ 2 Fig. 2 Functional block diagram .................................................................................................... 3 Fig. 3 Part numbering ..................................................................................................................... 5 Fig. 4 Memory expansion plan ...................................................................................................... 6 Fig. 5 740 Family CPU register structure .................................................................................... 7 Fig. 6 Register push and pop at interrupt generation and subroutine call ............................. 8 Fig. 7 Structure of CPU mode register ...................................................................................... 10 Fig. 8 Memory map diagram ........................................................................................................ 11 Fig. 9 Memory map of special function register (SFR) ............................................................ 12 Fig. 10 Port block diagram (1) .................................................................................................... 14 Fig. 11 Port block diagram (2) .................................................................................................... 15 Fig. 12 Structure of port I/O-related registers ........................................................................... 16 Fig. 13 Interrupt control ................................................................................................................ 18 Fig. 14 Structure of interrupt-related registers .......................................................................... 18 Fig. 15 Connection example when using key input interrupt and port P0 block diagram .. 19 Fig. 16 Structure of timer X mode register ............................................................................... 20 Fig. 17 Timer block diagram ........................................................................................................ 21 Fig. 18 Block diagram of clock synchronous serial I/O ........................................................... 22 Fig. 19 Operation of clock synchronous serial I/O function .................................................... 22 Fig. 20 Block diagram of UART serial I/O ................................................................................. 23 Fig. 21 Operation of UART serial I/O function .......................................................................... 23 Fig. 22 Structure of serial I/O control registers ........................................................................ 25 Fig. 23 USB function overview .................................................................................................... 26 Fig. 24 USB Function Control Circuit (USBFCC) block diagram ............................................ 27 Fig. 25 USB port external circuit (D0+, D0-, USBVREF, TrON) block diagram (4.0V ≤ VCC ≤ 5.25V) ........................................................................................................................... 28 Fig. 26 USB port external circuit (D0+, D0-, USBVREF, TrON) block diagram (3.0V ≤ VCC ≤ 4.0V) ............................................................................................................................. 28 Fig. 27 Example setting of buffer area beginning address ..................................................... 29 Fig. 28 Examples of interrupt source dependant buffer area offset address ....................... 29 Fig. 29 USB device interrupt control .......................................................................................... 31 Fig. 30 USB related registers ...................................................................................................... 32 Fig. 31 Structure of USB control register .................................................................................. 33 Fig. 32 Structure of USB function enable register ................................................................... 33 Fig. 33 Structure of USB function address register ................................................................. 34 Fig. 34 Structure of Frame number register Low ..................................................................... 34 Fig. 35 Structure of Frame number register High .................................................................... 34 Fig. 36 Structure of USB interrupt source enable register ...................................................... 35 Fig. 37 Structure of USB interrupt source register ................................................................... 36 Fig. 38 Structure of Endpoint index register ............................................................................. 36 Fig. 39 Structure of EP00 stage register ................................................................................... 37 Fig. 40 Structure of EP00 control register 1 ............................................................................. 37 Fig. 41 Structure of EP00 control register 2 ............................................................................. 37 Fig. 42 Structure of EP00 control register 3 ............................................................................. 38 Fig. 43 Structure of EP00 interrupt source register ................................................................. 38 List of figures |
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