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M38K24M7LHP Datasheet(PDF) 11 Page - Renesas Technology Corp

Part # M38K24M7LHP
Description  RENESAS 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M38K24M7LHP Datasheet(HTML) 11 Page - Renesas Technology Corp

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Rev.2.00
Oct 15, 2006
page 7 of 14
38K2 Group
REJ09B0338-0200
List of figures
Fig. 148 CPU rewrite mode set/release flowchart .................................................................. 103
Fig. 149 Program flowchart ........................................................................................................ 105
Fig. 150 Erase flowchart ............................................................................................................ 106
Fig. 151 Full status check flowchart and remedial procedure for errors ............................ 108
Fig. 152 Structure of ROM code protect control register ...................................................... 109
Fig. 153 ID code store addresses ............................................................................................ 110
Fig. 154 Pin connection diagram in standard serial I/O mode (1) ....................................... 114
Fig. 155 Timing for page read ................................................................................................... 116
Fig. 156 Timing for reading status register ............................................................................. 116
Fig. 157 Timing for clear status register .................................................................................. 117
Fig. 158 Timing for page program ............................................................................................ 117
Fig. 159 Timing for erase all blocks ......................................................................................... 118
Fig. 160 Timing for download .................................................................................................... 119
Fig. 161 Timing for version information output ....................................................................... 120
Fig. 162 Timing for Boot ROM area output ............................................................................. 120
Fig. 163 Timing for ID check ..................................................................................................... 121
Fig. 164 ID code storage addresses ........................................................................................ 121
Fig. 165 Full status check flowchart and remedial procedure for errors ............................ 124
Fig. 166 Example circuit application for standard serial I/O mode ...................................... 125
Fig. 167 Definition of A/D conversion accuracy ...................................................................... 127
Fig. 168 A/D conversion equivalent circuit .............................................................................. 130
Fig. 169 A/D conversion timing chart ....................................................................................... 130
CHAPTER 2 APPLICATION
Fig. 2.1.1 Memory map of registers related to I/O port .............................................................. 2
Fig. 2.1.2 Structure of Port Pi (i = 0 to 6) .................................................................................... 3
Fig. 2.1.3 Structure of Port Pi direction register (i = 0 to 6) ..................................................... 3
Fig. 2.1.4 Structure of Port P0 pull-up control register ............................................................... 4
Fig. 2.1.5 Structure of Port P5 pull-up control register ............................................................... 4
Fig. 2.2.1 Memory map of registers related to interrupt ............................................................. 8
Fig. 2.2.2 Structure of Interrupt request register 1 ...................................................................... 8
Fig. 2.2.3 Structure of Interrupt request register 2 ...................................................................... 9
Fig. 2.2.4 Structure of Interrupt control register 1 ....................................................................... 9
Fig. 2.2.5 Structure of Interrupt control register 2 ..................................................................... 10
Fig. 2.2.6 Structure of Interrupt edge selection register ........................................................... 10
Fig. 2.2.7 Interrupt operation diagram .......................................................................................... 12
Fig. 2.2.8 Changes of stack pointer and program counter upon acceptance of interrupt request
........................................................................................................................................ 13
Fig. 2.2.9 Time up to execution of interrupt processing routine .............................................. 14
Fig. 2.2.10 Timing chart after acceptance of interrupt request .............................................. 14
Fig. 2.2.11 Interrupt control diagram ............................................................................................ 15
Fig. 2.2.12 Example of multiple interrupts ................................................................................... 17
Fig. 2.2.13 Connection example and port P0 block diagram when using key input interrupt .
...................................................................................................................................... 19
Fig. 2.2.14 Registers setting related to key input interrupt (corresponding to Figure 2.2.13) .
...................................................................................................................................... 20
Fig. 2.2.15 Sequence of changing relevant register .................................................................. 21
Fig. 2.2.16 Sequence of check of interrupt request bit ............................................................. 22
Fig. 2.3.1 Memory map of registers related to timers ............................................................... 23
Fig. 2.3.2 Structure of Prescaler 12, Prescaler X ...................................................................... 23
Fig. 2.3.3 Structure of Timer 1 ..................................................................................................... 24
Fig. 2.3.4 Structure of Timer 2, Timer X ..................................................................................... 24


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