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M38K21MCLHP Datasheet(PDF) 9 Page - Renesas Technology Corp |
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M38K21MCLHP Datasheet(HTML) 9 Page - Renesas Technology Corp |
9 / 358 page Rev.2.00 Oct 15, 2006 page 5 of 14 38K2 Group REJ09B0338-0200 List of figures Fig. 44 Structure of EP00 interrupt source register ................................................................. 39 Fig. 45 Structure of EP00 byte number register ....................................................................... 40 Fig. 46 Structure of EP00 buffer area set register ................................................................... 40 Fig. 47 Structure of EP01 set register ....................................................................................... 41 Fig. 48 Structure of EP01 control register 1 ............................................................................. 41 Fig. 49 Structure of EP01 control register 2 ............................................................................. 42 Fig. 50 Structure of EP01 control register 3 ............................................................................. 42 Fig. 51 Structure of EP01 interrupt source register ................................................................. 42 Fig. 52 Structure of EP01 byte number register 0 ................................................................... 43 Fig. 53 Structure of EP01 byte number register 1 ................................................................... 43 Fig. 54 Structure of EP01 MAX. packet size register .............................................................. 43 Fig. 55 Structure of EP01 buffer area set register ................................................................... 44 Fig. 56 Structure of EP02 set register ....................................................................................... 45 Fig. 57 Structure of EP02 control register 1 ............................................................................. 45 Fig. 58 Structure of EP02 control register 2 ............................................................................. 46 Fig. 59 Structure of EP02 control register 3 ............................................................................. 46 Fig. 60 Structure of EP02 interrupt source register ................................................................. 46 Fig. 61 Structure of EP02 byte number register 0 ................................................................... 47 Fig. 62 Structure of EP02 byte number register 1 ................................................................... 47 Fig. 63 Structure of EP02 MAX. packet size register .............................................................. 47 Fig. 64 Structure of EP02 buffer area set register ................................................................... 48 Fig. 65 Structure of EP03 set register ....................................................................................... 49 Fig. 66 Structure of EP03 control register 1 ............................................................................. 49 Fig. 67 Structure of EP03 control register 2 ............................................................................. 50 Fig. 68 Structure of EP03 control register 3 ............................................................................. 50 Fig. 69 Structure of EP03 interrupt source register ................................................................. 50 Fig. 70 Structure of EP03 byte number register 0 ................................................................... 51 Fig. 71 Structure of EP03 byte number register 1 ................................................................... 51 Fig. 72 Structure of EP03 MAX. packet size register .............................................................. 51 Fig. 73 Structure of EP03 buffer area set register ................................................................... 52 Fig. 74 Structure of EP10 stage register ................................................................................... 53 Fig. 75 Structure of EP10 control register 1 ............................................................................. 53 Fig. 76 Structure of EP10 control register 2 ............................................................................. 53 Fig. 77 Structure of EP10 control register 3 ............................................................................. 54 Fig. 78 Structure of EP10 interrupt source register ................................................................. 54 Fig. 79 Structure of EP10 byte number register ....................................................................... 55 Fig. 80 Structure of EP10 buffer area set register ................................................................... 55 Fig. 81 Structure of EP11 set register ....................................................................................... 56 Fig. 82 Structure of EP11 control register 1 ............................................................................. 56 Fig. 83 Structure of EP11 control register 2 ............................................................................. 56 Fig. 84 Structure of EP11 interrupt source register ................................................................. 57 Fig. 85 Structure of EP11 byte number register ....................................................................... 57 Fig. 86 Structure of EP11 buffer area set register ................................................................... 57 Fig. 87 HUB functions ................................................................................................................... 58 Fig. 88 HUB function control circuit block diagram .................................................................. 59 Fig. 89 Block diagram of USB down-port peripheral circuits (D1+, D1-) .............................. 60 Fig. 90 Block diagram of USB down-port peripheral circuits (D2+, D2-) .............................. 60 Fig. 91 USB HUB interrupt control ............................................................................................. 61 Fig. 92 HUB related registers ...................................................................................................... 62 Fig. 93 Structure of HUB interrupt source enable register ..................................................... 63 Fig. 94 Structure of HUB interrupt source register .................................................................. 63 Fig. 95 Structure of HUB downstream port index register ...................................................... 64 |
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