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CD-700-KAF-GCB-77.760 Datasheet(PDF) 5 Page - Vectron International, Inc |
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CD-700-KAF-GCB-77.760 Datasheet(HTML) 5 Page - Vectron International, Inc |
5 / 14 page CD-700, VCXO Based PLL Vectron International, 267 Lowell Rd, Hudson NH 03051-4916 Tel: 1-88-VECTRON-1 • Web: www.vectron.com Page 5 of 14 Rev : 06Apr08 VDD 0V 0 +π −π Relative Phase ( θ e) VDD/2 Vd Gain Slope = VDD/ 2π Figure 5. Open Loop Phase Detector Transfer Curve Recovered Clock and Data Alignment Outputs The CD-700 is designed to recover an embedded clock from an NRZ data signal and retime it with a data pattern. In this application, the VCXO frequency is exactly the same frequency as the NRZ data rate and the outputs are taken off Pin 9 (RCLK), and Pin 10 (RDATA). Under locked conditions, the falling edge of RCLK is centered in the RDATA pattern. Also, there is a 1.5 clock cycle delay between DATAIN and RDATA. Figure 6 shows the relationship between the DATAIN, CLKIN, RDATA and RCLK. Figure 6. Clock and Data Timing Relationships for the NRZ data Other RZ encoding schemes such as Manchester or AMI can be accomodated by using a CD-700 at twice the baud rate. Loss of Signal, LOS and LOSIN The LOS circuit provides an output alarm flag when the DATAIN input signal is lost. The LOS output is normally a logic low and is set to a logic high after 256 consecutive clock periods on CLKIN with no detected DATAIN transitions. This signal can be used to either flag external alarm circuits and/or drive the CD-700’s LOSIN input. When LOSIN is set to a logic high, the VCXO control voltage (pin 16) is switched to an internal voltage which sets OUT1 and OUT2 to center frequency +/-75ppm. Also, LOS automatically closes the op amp feedback which means the op-amp is a unity gain buffer and will produce a DC voltage equal to the +op amp voltage (pin 15), usually VDD/2. Data1 Clock In CLKIN Data In DATAIN Recovered Data RDATA Recovered Clock RCLK |
Similar Part No. - CD-700-KAF-GCB-77.760 |
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Similar Description - CD-700-KAF-GCB-77.760 |
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