Rev. 0

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Page 10 of 20

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August 2008

AD1989B

Table 4. Pin Function Descriptions

Mnemonic

Pin No.

Function

Description

DIGITAL INTERFACE

SDATA_OUT

BIT_CLK

SDATA_IN

SYNC

RESET

5

6

8

10

11

I

I

I/O

I

I

Link Serial Data Output. Clocked on both edges of BIT_CLK.

Link Bit Clock. 24.000 MHz serial data clock.

Link Serial Data Input. AD1989B output stream clocked only on one edge of BIT_CLK.

Link Frame Sync.

Link Reset. Master hardware reset.

DIGITAL I/O

S/PDIF-OUT_2/GPIO_0

S/PDIF_IN/GPIO_1

S/PDIF-OUT_1/GPIO_2

2

47

48

I/O

I/O

I/O

S/PDIF Out or GPIO. Supports S/PDIF output as primary function.

S/PDIF Input/General-Purpose Input/Output Pin. Supports S/PDIF input as primary

function.

S/PDIF_OUT or GPIO. Supports S/PDIF output as primary function.

JACK SENSE

SENSE_A/SRC_B

SENSE_B/SRC_A

SENSE_C

13

34

30

I/O

I/O

I

JACK Sense A-D Input/Sense B drive.

JACK Sense E-H Input/Sense A drive.

JACK Sense CD/Line inputs.

ANALOG I/O

PCBEEP

Port-E_L

Port-E_R

Port-F_L

Port-F_R

CD_L/LINE_IN_L

CD_GND

CD_R/LINE_IN_R

Port-B_L

Port-B_R

Port-C_L

Port-C_R

Port-D_L

Port-D_R

Port-A_L

MONO_OUT

Port-A_R

Port-G_L

Port-G_R

Port-H_L

Port-H_R

12

14

15

16

17

18

19

20

21

22

23

24

35

36

39

40

41

43

44

45

46

LI

LI, MIC, LO, SWAP

LI, MIC, LO, SWAP

LO

LO

LI

LI

LI

LI, MIC, HP, LO

LI, MIC, HP, LO

LI, MIC, LO

LI, MIC, LO

LI, HP, LO

LI, HP, LO

LI, MIC, HP, LO

LO

LI, MIC, HP, LO

LO, SWAP

LO, SWAP

LO

LO

Monaural Input From System for Analog PCBeep.

Auxiliary Input/Output Left Channel.

Auxiliary Input/Output Right Channel.

Auxiliary Input/Surround Rear (5.1) Left Channel.

Auxiliary Input/Surround Rear (5.1) Right Channel.

CD Audio Left Channel.

CD Audio Analog Ground Reference (for Differential CD Input). Must be connected to

AGND via 0.1

μF capacitor if not in use as CD_GND.

CD Audio Right Channel.

Front Panel Stereo MIC/Line-In.

Front Panel Stereo MIC/Line-In.

Rear Panel Stereo MIC/Line-In.

Rear Panel Stereo MIC/Line-In.

Rear Panel Headphone/Line-Out.

Rear Panel Headphone/Line-Out.

Front Panel Headphone/Line-Out.

Monaural Output to Internal Speaker or Telephony Subsystem Speakerphone.

Front Panel Headphone/Line-Out.

Rear Panel C/LFE Output.

Rear Panel C/LFE Output.

Rear Panel Surround Center/Side (7.1).

Rear Panel Surround Center/Side (7.1).

FILTER/REFERENCE

MIC_BIAS-B/EAPD-B

MIC_BIAS-C/EAPD-C

MIC_BIAS-E/EAPD-E

MIC_BIAS-D/EAPD-D

MIC_BIAS-A/EAPD-A

VREF_FILT

28

29

31

32

37

27

1

O

O

O

O

O

O

O

Switchable Microphone Bias. For use with Port B (Pins 21, 22).

Switchable Microphone Bias. For use with Port C (Pins 23, 24).

Switchable Microphone Bias. For use with Port E (Pins 14, 15).

Switchable Microphone Bias. For use with Port D (Pins 35, 36)

Switchable Microphone Bias. For use with Port A (Pins 39, 41)

All MIC_BIAS pins are capable of:

High-Z, 0 V, 1.65 V, 3.78 V, and 3.95 V (with 5.0 V on Pin 33)

High-Z, 0 V, 1.65 V, 2.86 V, and 3.00 V (with 3.3 V on Pin 33).

Voltage Reference Filter.

CAUTION: DO NOT APPLY 3.3 V TO THIS PIN!

Filter connection for internal core voltage regulator.

This pin must be connected to filter caps: 10

μF, 1.0 μF, and 0.1 μF connected in

The symbols used in this table are defined as: I = input, O = output, LI = line level input, LO = line level output, HP = output capable of driving

headphone load, MIC = input supports microphones with MIC bias and boost amplifier, SWAP = outputs can swap L/R channels (typically used

to support C/LFE or shared C/LFE function).