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AD7401A Datasheet(PDF) 5 Page - Analog Devices |
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AD7401A Datasheet(HTML) 5 Page - Analog Devices |
5 / 20 page AD7401A Rev. 0 | Page 5 of 20 TIMING SPECIFICATIONS VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, TA = −40°C to +125°C, unless otherwise noted. Table 2. Parameter1 Limit at TMIN, TMAX Unit Description fMCLKIN2, 3 20 MHz max Master clock input frequency 5 MHz min Master clock input frequency t14 25 ns max Data access time after MCLKIN rising edge t24 15 ns min Data hold time after MCLKIN rising edge t3 0.4 × tMCLKIN ns min Master clock low time t4 0.4 × tMCLKIN ns min Master clock high time 1 Sample tested during initial release to ensure compliance. 2 Mark space ratio for clock input is 40/60 to 60/40 for fMCLKIN ≤ 16 MHz and 48/52 to 52/48 for 16 MHz < fMCLKIN < 20 MHz. 3 VDD1 = VDD2 = 5 V ± 5% for fMCLKIN > 16 MHz to 20 MHz. 4 Measured with the load circuit of and defined as the time required for the output to cross 0.8 V or 2.0 V. Figure 2 200µA IOL 200µA IOH 1.6V TO OUTPUT PIN CL 25pF Figure 2. Load Circuit for Digital Output Timing Specifications MCLKIN MDAT t1 t2 t4 t3 Figure 3. Data Timing |
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