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AD7401AYRWZ Datasheet(PDF) 4 Page - Analog Devices |
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AD7401AYRWZ Datasheet(HTML) 4 Page - Analog Devices |
4 / 20 page AD7401A Rev. 0 | Page 4 of 20 Parameter Y Version1, 2 Unit Test Conditions/Comments Min Typ Max LOGIC OUTPUTS Output High Voltage, VOH VDD2 − 0.1 V IO = −200 μA Output Low Voltage, VOL 0.4 V IO = +200 μA POWER REQUIREMENTS VDD1 4.5 5.5 V VDD2 3 5.5 V IDD15 10 12 mA VDD1 = 5.5 V IDD26 7 9 mA VDD2 = 5.5 V 3 4 mA VDD2 = 3.3 V Power Dissipation 93.5 mW VDD1 = VDD2 = 5.5 V 1 For fMCLK > 16 MHz to 20 MHz, mark space ratio is 48/52 to 52/48, VDD1 = VDD2 = 5 V ± 5%, and TA = −40°C to +85°C. 2 All voltages are relative to their respective ground. 3 See the section. Terminology 4 Sample tested during initial release to ensure compliance. 5 See . Figure 15 6 See . Figure 17 |
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