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ADIS16300 Datasheet(PDF) 4 Page - Analog Devices |
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ADIS16300 Datasheet(HTML) 4 Page - Analog Devices |
4 / 16 page ![]() ADIS16300 Rev. 0 | Page 4 of 16 Parameter Conditions Min Typ Max Unit ADC INPUT Resolution 12 Bits Integral Nonlinearity ±2 LSB Differential Nonlinearity ±1 LSB Offset Error ±4 LSB Gain Error ±2 LSB Input Range 0 +3.3 V Input Capacitance During acquisition 20 pF DAC OUTPUT 5 kΩ/100 pF to GND Resolution 12 Bits Relative Accuracy For Code 101 to Code 4095 ±4 LSB Differential Nonlinearity ±1 LSB Offset Error ±5 mV Gain Error ±0.5 % Output Range 0 +3.3 V Output Impedance 2 Ω Output Settling Time 10 μs LOGIC INPUTS1 Input High Voltage, VINH 2.0 V Input Low Voltage, VINL 0.8 V CS signal to wake up from sleep mode 0.55 V CS Wake-Up Pulse Width 20 μs Logic 1 Input Current, IINH VIH = 3.3 V ±0.2 ±10 μA Logic 0 Input Current, IINL VIL = 0 V All Pins Except RST −40 −60 μA RST Pin −1 mA Input Capacitance, CIN 10 pF DIGITAL OUTPUTS1 Output High Voltage, VOH ISOURCE = 1.6 mA 2.4 V Output Low Voltage, VOL ISINK = 1.6 mA 0.4 V FLASH MEMORY Endurance2 10,000 Cycles Data Retention3 TJ = 85°C 20 Years FUNCTIONAL TIMES4 Time until data is available Power-On Start-up Time Normal mode, SMPL_PRD ≤ 0x09 180 ms Low power mode, SMPL_PRD ≥ 0x0A 245 ms Reset Recovery Time Normal mode, SMPL_PRD ≤ 0x09 55 ms Low power mode, SMPL_PRD ≥ 0x0A 120 ms Sleep Mode Recovery Time 2.5 ms Flash Memory Test Time Normal mode, SMPL_PRD ≤ 0x09 17 ms Low power mode, SMPL_PRD ≥ 0x0A 90 ms Automatic Self-Test Time 12 ms CONVERSION RATE SMPL_PRD = 0x01 to 0xFF 0.413 819.2 SPS Clock Accuracy ±3 % Sync Input Clock 1.2 kHz POWER SUPPLY Operating voltage range, VCC 4.75 5.0 5.25 V Power Supply Current Low power mode at 25°C 18 mA Normal mode at 25°C 42 mA Sleep mode at 25°C 500 μA 1 The digital I/O signals are driven by an internal 3.3 V supply, and the inputs are 5 V tolerant. 2 Endurance is qualified as per JEDEC Standard 22, Method A117, and measured at −40°C, +25°C, +85°C, and +125°C. 3 The retention lifetime equivalent is at a junction temperature (TJ) of 85°C as per JEDEC Standard 22, Method A117. Retention lifetime decreases with junction temperature. 4 These times do not include thermal settling and internal filter response times (330 Hz bandwidth), which may impact overall accuracy. |
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