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TLV320ADC3101IRGET Datasheet(PDF) 7 Page - Texas Instruments |
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TLV320ADC3101IRGET Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 84 page  AUDIO DATA SERIAL INTERFACE TIMING DIAGRAMS WCLK BCLK DOUT t (DO-BCLK) d t (DO-WS) d t (WS) d TLV320ADC3101 www.ti.com ........................................................................................................................................................................................... SLAS553 – NOVEMBER 2008 All specifications at 25°C, DVDD = 1.8 V IOVDD = 1.8 V IOVDD = 3.3 V PARAMETER UNIT MIN MAX MIN MAX td(WS) BCLK/WCLK delay time 20 15 ns td(DO-WS) BCLK/WCLK to DOUT delay time 25 20 ns td(DO-BCLK) BCLK to DOUT delay time 20 15 ns tr Rise time 20 15 ns tf Fall time 20 15 ns NOTE: All timing specifications are measured at characterization but not tested at final test. Figure 2. I2S/LJF/RJF Timing in Master Mode Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s) :TLV320ADC3101 |
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