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P89LPC935FHN Datasheet(PDF) 9 Page - NXP Semiconductors |
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P89LPC935FHN Datasheet(HTML) 9 Page - NXP Semiconductors |
9 / 75 page P89LPC933_934_935_936_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 26 November 2008 9 of 75 NXP Semiconductors P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core P2.0 to P2.7 I/O Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. During reset Port 2 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 8.13.1 “Port configurations” and Table 11 “Static characteristics” for details. All pins have Schmitt trigger inputs. Port 2 also provides various special functions as described below: P2.0/ICB/ DAC0/AD03 1 25 I/O P2.0 — Port 2 bit 0. I ICB — Input Capture B. (P89LPC935/936) I DAC0 — Digital-to-analog converter output. I AD03 — ADC0 channel 3 analog input. (P89LPC935/936) P2.1/OCD/ AD02 2 26 I/O P2.1 — Port 2 bit 1. O OCD — Output Compare D. (P89LPC935/936) I AD02 — ADC0 channel 2 analog input. (P89LPC935/936) P2.2/MOSI 13 9 I/O P2.2 — Port 2 bit 2. I/O MOSI — SPI master out slave in. When configured as master, this pin is output; when configured as slave, this pin is input. P2.3/MISO 14 10 I/O P2.3 — Port 2 bit 3. I/O MISO — When configured as master, this pin is input, when configured as slave, this pin is output. P2.4/SS 15 11 I/O P2.4 — Port 2 bit 4. I SS — SPI Slave select. P2.5/ SPICLK 16 12 I/O P2.5 — Port 2 bit 5. I/O SPICLK — SPI clock. When configured as master, this pin is output; when configured as slave, this pin is input. P2.6/OCA 27 23 I/O P2.6 — Port 2 bit 6. O OCA — Output Compare A. (P89LPC935/936) P2.7/ICA 28 24 I/O P2.7 — Port 2 bit 7. I ICA — Input Capture A. (P89LPC935/936) Table 4. Pin description …continued Symbol Pin Type Description TSSOP28, PLCC28 HVQFN28 |
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