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P89V662FBC Datasheet(PDF) 8 Page - NXP Semiconductors |
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P89V662FBC Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 89 page P89V660_662_664_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 November 2008 8 of 89 NXP Semiconductors P89V660/662/664 80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI P3[2]/INT0 8 14 I P3[2] — Port 3 bit 2. I INT0 — External interrupt 0 input. P3[3]/INT1 9 15 I P3[3] — Port 3 bit 3. I INT1 — External interrupt 1 input P3[4]/T0/CEX3 10 16 I/O P3[4] — Port 3 bit 4. I T0 — External count input to Timer/Counter 0. I/O CEX3 — Capture/compare external I/O for PCA Module 3. P3[5]/T1/CEX4 11 17 I/O P3[5] — Port 3 bit 5. I T1 — External count input to Timer/Counter 1 I/O CEX4 — Capture/compare external I/O for PCA Module 4 P3[6]/WR 12 18 O P3[6] — Port 3 bit 6. O WR — External data memory write strobe P3[7]/RD 13 19 O P3[7] — Port 3 bit 7. O RD — External data memory read strobe. P4[0] to P4[3] I/O with internal pull-up Port 4: Port 4 is a 4-bit bidirectional I/O port with internal pull-ups. Port 4 pins are pulled HIGH by the internal pull-ups when ‘1’s are written to them and can be used as inputs in this state. As inputs, Port 4 pins that are externally pulled LOW will source current (IIL) because of the internal pull-ups. P4[0]/SCL_1/ SCK 17 23 I/O P4[0] — Port 4 bit 0. I/O SCL_1 — Second I2C-bus serial clock input/output I/O SCK — Serial clock input/output for SPI P4[1]/SDA_1/ MISO 28 34 I/O P4[1] — Port 4 bit 1. I/O SDA_1 — Second I2C-bus serial data input/output I/O MISO — Master input/slave output for SPI P4[2]/MOSI 39 1 I/O P4[2] — Port 4 bit 2. I/O MOSI — Master output/slave input for SPI P4[3]/SS 6 12 I P4[3] — Port 4 bit 3. I SS — Slave select input for SPI PSEN 26 32 I/O Program Store Enable: PSEN is the read strobe for external program memory. When the device is executing from internal program memory, PSEN is inactive (HIGH). When the device is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. RST 4 10 I Reset: While the oscillator is running, a HIGH logic state on this pin for two machine cycles will reset the device. EA 29 35 I External Access Enable: EA must be connected to VSS in order to enable the device to fetch code from the external program memory. EA must be strapped to VDD for internal program execution. Table 3. Pin description …continued Symbol Pin Type Description TQFP44 PLCC44 |
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