PCA9544A_3

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 03 — 24 November 2008

6 of 27

NXP Semiconductors

PCA9544A

6.

Functional description

Refer to Figure 1 “Block diagram”.

6.1 Device addressing

Following a START condition the bus master must output the address of the slave it is

accessing. The address of the PCA9544A is shown in Figure 5. To conserve power, no

internal pull-up resistors are incorporated on the hardware selectable address pins and

they must be pulled HIGH or LOW.

The last bit of the slave address defines the operation to be performed. When set to

logic 1 a read is selected, while a logic 0 selects a write operation.

6.2 Control register

Following the successful acknowledgement of the slave address, the bus master will send

a byte to the PCA9544A which will be stored in the Control register. If multiple bytes are

received by the PCA9544A, it will save the last byte received. This register can be written

6.2.1 Control register definition

A SCx/SDx downstream pair, or channel, is selected by the contents of the control

register. This register is written after the PCA9544A has been addressed. The 3 LSBs of

the control byte are used to determine which channel is to be selected. When a channel is

This ensures that all SCx/SDx lines will be in a HIGH state when the channel is made

active, so that no false conditions are generated at the time of connection.

Fig 5.

Slave address

002aab189

1

1

1

0

A2

A1

A0 R/W

fixed

hardware

selectable

Fig 6.

Control register

002aae297

INT3 INT2 INT1 INT0

X

B2

B1

B0

interrupt bits

(read only)

channel selection bits

(read/write)

76543210

bit

enable bit