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PEMD2 Datasheet(PDF) 3 Page - NXP Semiconductors |
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PEMD2 Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 16 page PEMD2_PIMD2_PUMD2_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 24 September 2008 3 of 16 NXP Semiconductors PEMD2; PIMD2; PUMD2 NPN/PNP resistor-equipped transistors; R1 = 22 k Ω, R2 = 22 kΩ 4. Marking [1] * = -: made in Hong Kong * = p: made in Hong Kong * = t: made in Malaysia * = W: made in China 5. Limiting values Table 5. Marking codes Type number Marking code[1] PEMD2 D4 PIMD2 M5 PUMD2 D*2 Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Per transistor; for the PNP transistor with negative polarity VCBO collector-base voltage open emitter - 50 V VCEO collector-emitter voltage open base - 50 V VEBO emitter-base voltage open collector - 10 V VI input voltage TR1 positive - +40 V negative - −10 V input voltage TR2 positive - +10 V negative - −40 V IO output current - 100 mA ICM peak collector current single pulse; tp ≤ 1ms - 100 mA Ptot total power dissipation Tamb ≤ 25 °C [1] PEMD2 (SOT666) [2] - 200 mW PIMD2 (SOT457) - 300 mW PUMD2 (SOT363) - 200 mW Tj junction temperature - 150 °C Tamb ambient temperature −65 +150 °C Tstg storage temperature −65 +150 °C |
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