CS2100-OTP

DS841PP1

2

TABLE OF CONTENTS

1. PIN DESCRIPTION ................................................................................................................................. 4

2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 5

3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6

RECOMMENDED OPERATING CONDITIONS .................................................................................... 6

ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6

DC ELECTRICAL CHARACTERISTICS ................................................................................................ 6

AC ELECTRICAL CHARACTERISTICS ................................................................................................ 7

4. ARCHITECTURE OVERVIEW ............................................................................................................... 8

4.1 Delta-Sigma Fractional-N Frequency Synthesizer ........................................................................... 8

4.2 Hybrid Analog-Digital Phase Locked Loop ...................................................................................... 8

5. APPLICATIONS ................................................................................................................................... 10

5.1 One Time Programmability ............................................................................................................ 10

5.2 Timing Reference Clock Input ........................................................................................................ 10

5.2.1 Internal Timing Reference Clock Divider ............................................................................... 10

5.2.2 Crystal Connections (XTI and XTO) ...................................................................................... 11

5.2.3 External Reference Clock (REF_CLK) .................................................................................. 11

5.3 Frequency Reference Clock Input, CLK_IN ................................................................................... 11

5.3.1 CLK_IN Skipping Mode ......................................................................................................... 11

5.3.2 Adjusting the Minimum Loop Bandwidth for CLK_IN ............................................................ 13

5.4 Output to Input Frequency Ratio Configuration ............................................................................. 14

5.4.1 User Defined Ratio (RUD) ..................................................................................................... 14

5.4.2 Manual Ratio Modifier (R-Mod) ............................................................................................. 15

5.4.3 Automatic Ratio Modifier (Auto R-Mod) ................................................................................ 15

5.4.4 Effective Ratio (REFF) .......................................................................................................... 16

5.4.5 Ratio Configuration Summary ............................................................................................... 16

5.5 PLL Clock Output ........................................................................................................................... 17

5.6 Auxiliary Output .............................................................................................................................. 18

5.7 Mode Pin Functionality ................................................................................................................... 18

5.7.1 M1 and M0 Mode Pin Functionality ....................................................................................... 18

5.7.2 M2 Mode Pin Functionality .................................................................................................... 19

5.7.2.1 M2 Configured as Output Disable .............................................................................. 19

5.7.2.2 M2 Configured as R-Mod Enable .............................................................................. 19

5.7.2.3 M2 Configured as Auto R-Mod Enable ...................................................................... 19

5.7.2.4 M2 Configured as AuxOutSrc Override ..................................................................... 19

5.8 Clock Output Stability Considerations ............................................................................................ 20

5.8.1 Output Switching ................................................................................................................... 20

5.8.2 PLL Unlock Conditions .......................................................................................................... 20

6. PARAMETER DESCRIPTIONS ........................................................................................................... 21

6.1 Modal Configuration Sets ............................................................................................................... 21

6.1.1 R-Mod Selection (RModSel[1:0]) ...........................................................................................21

6.1.2 Auxiliary Output Source Selection (AuxOutSrc[1:0]) ............................................................. 22

6.1.3 Auto R-Modifier Enable (AutoRMod) ..................................................................................... 22

6.2 Ratio 0 - 3 ...................................................................................................................................... 22

6.3 Global Configuration Parameters ................................................................................................... 22

6.3.1 Clock Skip Enable (ClkSkipEn) ............................................................................................. 22

6.3.2 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 23

6.3.3 Reference Clock Input Divider (RefClkDiv[1:0]) .................................................................... 23

6.3.4 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 23

6.3.5 Low-Frequency Ratio Configuration (LFRatioCfg) ................................................................ 23

6.3.6 M2 Pin Configuration (M2Config[2:0]) ................................................................................... 24

6.3.7 Clock Input Bandwidth (ClkIn_BW[2:0]) ................................................................................ 24

7. CALCULATING THE USER DEFINED RATIO .................................................................................... 25