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CS4382 Datasheet(PDF) 9 Page - Cirrus Logic |
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CS4382 Datasheet(HTML) 9 Page - Cirrus Logic |
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9 / 42 page  DS514F2 9 CS4382 SWITCHING CHARACTERISTICS (For KQZ TA = -10°C to +70°C; VLS = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLS, CL = 30 pF) Notes: 15. See Table 5 on page 27 for suggested MCLK frequencies. 16. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled. 17. The higher frequency LRCK must be an exact integer multiple (1, 2, or 4) of the lower frequency LRCK. . Parameters Symbol Min Typ Max Units MCLK Frequency (Note 15) Single-Speed Mode 1.024 - 51.2 MHz Double-Speed Mode 6.400 - 51.2 MHz Quad-Speed Mode 6.400 - 51.2 MHz MCLK Duty Cycle 405060 % Input Sample Rate Single-Speed Mode Double-Speed Mode Quad-Speed Mode Fs Fs Fs 4 50 100 - - - 50 100 200 kHz kHz kHz LRCK Duty Cycle 45 50 55 % SCLK Pulse Width Low tsclkl 20 - - ns SCLK Pulse Width High tsclkh 20 - - ns SCLK Period tsclkw -- ns (Note 16) tsclkw -- ns SCLK rising to LRCK edge delay tslrd 20 - - ns SCLK rising to LRCK edge setup time tslrs 20 - - ns SDATA valid to SCLK rising setup time tsdlrs 20 - - ns SCLK rising to SDATA hold time tsdh 20 - - ns LRCK1 to LRCK2 frequency ratio (Note 17) 0.25 1.00 4.00 2 MCLK ----------------- 4 MCLK ----------------- sclkh t slrs t slrd t sdlrs t sdh t sclkl t SDATA SCLK LRCK Figure 1. Serial Mode Input Timing |
Similar Part No. - CS4382_08 |
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Similar Description - CS4382_08 |
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