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BQ24109RHLTG4 Datasheet(PDF) 6 Page - Texas Instruments

Part # BQ24109RHLTG4
Description  SYNCHRONOUS SWITCHMODE, LI-ION AND LI-POLYMER CHARGE-MANAGEMENT IC WITH INTEGRATED POWER FETs (bqSWITCHER??
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

BQ24109RHLTG4 Datasheet(HTML) 6 Page - Texas Instruments

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bq24100
,, bq24103,, bq24103A
bq24104, bq24105, bq24108, bq24109
bq24113, bq24113A, bq24115
SLUS606N – JUNE 2004 – REVISED NOVEMBER 2008 .................................................................................................................................................. www.ti.com
TERMINAL FUNCTIONS
TERMINAL
bq24100,
bq24103,
I/O
DESCRIPTION
bq24113,
NAME
bq24108,
bq24103A
bq24105
bq24115
bq24113A
bq24109
bq24104
Battery voltage sense input. Bypass it with a 0.1
µF capacitor to PGND if
BAT
14
14
14
14
14
I
there are long inductive leads to battery.
Charger enable input. This active low input, if set high, suspends charge
CE
16
16
16
16
16
I
and places the device in the low-power sleep mode. Do not pull up this
input to VTSB.
Available on parts with fixed output voltage. Ground or float for single-cell
CELLS
13
13
I
operation (4.2 V). For two-cell operation (8.4 V) pull up this pin with a
resistor to VCC.
Charge mode selection: low for precharge as set by ISET2 pin and high
CMODE
7
7
I
(pull up to VTSB or <7 V) for fast charge as set by ISET1.
Output voltage analog feedback adjustment. Connect the output of a
FB
13
13
I
resistive voltage divider powered from the battery terminals to this node to
adjust the output battery voltage regulation.
IN
3, 4
3, 4
3, 4
3, 4
3, 4
I
Charger input voltage.
Charger current set point 1 (fast charge). Use a resistor to ground to set
ISET1
8
8
8
8
8
I/O
this value.
Charge current set point 2 (precharge and termination), set by a resistor
connected to ground. A low-level CMODE signal selects the ISET2 charge
ISET2
9
9
9
9
9
I/O
rate, but if the battery voltage reaches the regulation set point,
bqSWITCHER changes to voltage regulation regardless of CMODE input.
N/C
13
19
19
-
No connection. This pin must be left floating in the application.
1
1
1
1
1
O
Charge current output inductor connection. Connect a zener TVS diode
OUT
between OUT pin and PGND pin to clamp the voltage spike to protect the
20
20
20
20
20
O
power MOSFETs during abnormal conditions.
Power-good status output (open drain). The transistor turns on when a
PG
5
5
5
5
5
O
valid VCC is detected. It is turned off in the sleep mode. PG can be used to
drive a LED or communicate with a host processor.
PGND
17,18
17,18
17,18
17,18
17, 18
Power ground input
Charge current-sense input. Battery current is sensed via the voltage drop
SNS
15
15
15
15
15
I
developed on this pin by an external sense resistor in series with the
battery pack. A 0.1-
µF capacitor to PGND is required.
Charge status 1 (open-drain output). When the transistor turns on
STAT1
2
2
2
2
2
O
indicates charge in process. When it is off and with the condition of STAT2
indicates various charger conditions (See Table 1)
Charge status 2 (open-drain output). When the transistor turns on
STAT2
19
19
19
O
indicates charge is done. When it is off and with the condition of STAT1
indicates various charger conditions (See Table 1)
Temperature sense input. This input monitors its voltage against an
internal threshold to determine if charging is allowed. Use an NTC
TS
12
12
12
12
12
I
thermistor and a voltage divider powered from VTSB to develop this
voltage. (See Figure 10)
Timer and termination control. Connect a capacitor from this node to GND
TTC
7
7
7
I
to set the bqSWITCHER timer. When this input is low, the timer and
termination detection are disabled.
VCC
6
6
6
6
6
I
Analog device input. A 0.1
µF capacitor to VSS is required.
VSS
10
10
10
10
10
Analog ground input
TS internal bias regulator voltage. Connect capacitor (with a value
VTSB
11
11
11
11
11
O
between a 0.1-
µF and 1-µF) between this output and VSS.
There is an internal electrical connection between the exposed thermal
pad and VSS. The exposed thermal pad must be connected to the same
Exposed
potential as the VSS pin on the printed circuit board. The power pad can
Thermal
Pad
Pad
Pad
Pad
Pad
be used as a star ground connection between VSS and PGND. A common
Pad
ground plane may be used. VSS pin must be connected to ground at all
times.
6
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Copyright © 2004–2008, Texas Instruments Incorporated
Product Folder Link(s): bq24100 bq24103 bq24103A bq24104 bq24105 bq24108 bq24109 bq24113 bq24113A
bq24115


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