Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

SMCP-67206HV-15SCC Datasheet(PDF) 4 Page - ATMEL Corporation

Part # SMCP-67206HV-15SCC
Description  Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO
Download  20 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

SMCP-67206HV-15SCC Datasheet(HTML) 4 Page - ATMEL Corporation

  SMCP-67206HV-15SCC Datasheet HTML 1Page - ATMEL Corporation SMCP-67206HV-15SCC Datasheet HTML 2Page - ATMEL Corporation SMCP-67206HV-15SCC Datasheet HTML 3Page - ATMEL Corporation SMCP-67206HV-15SCC Datasheet HTML 4Page - ATMEL Corporation SMCP-67206HV-15SCC Datasheet HTML 5Page - ATMEL Corporation SMCP-67206HV-15SCC Datasheet HTML 6Page - ATMEL Corporation SMCP-67206HV-15SCC Datasheet HTML 7Page - ATMEL Corporation SMCP-67206HV-15SCC Datasheet HTML 8Page - ATMEL Corporation SMCP-67206HV-15SCC Datasheet HTML 9Page - ATMEL Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 20 page
background image
4
M67206H
4143J–AERO–04/07
Write Enable (W)
A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set.
Data set-up and hold times must be maintained in the rise time of the leading edge of
the Write Enable (W). Data is stored sequentially in the Ram array, regardless of any
current read operation.
Once half the memory is filled, and during the falling edge of the next write operation,
the Half-Full Flag (HF) will be set to low and remain in this state until the difference
between the write and read pointers is less than or equal to half of the total available
memory in the device. The Half-Full Flag (HF) is then reset by the rising edge of the
read operation.
To prevent data overflow, the Full Flag (FF) will go low, inhibiting further write opera-
tions. On completion of a valid read operation, the Full Flag (FF) will go high after TRFF,
allowing a valid write to begin. When the FIFO stack is full, the internal write pointer is
blocked from W, so that external changes to W will have no effect on the full FIFO stack.
Read Enable (R)
A read cycle is initiated on the falling edge of the Read Enable (R) provided that the
Empty Flag (EF) is not set. The data is accessed on a first-in/first-out basis, not includ-
ing any current write operations. After Read Enable (R) goes high, the Data Outputs (Q0
- Q8) will return to a high impedance state until the next Read operation. When all the
data in the FIFO stack has been read, the Empty Flag (EF) will go low, allowing the
“final” read cycle, but inhibiting further read operations while the data outputs remain in
a high impedance state. Once a valid write operation has been completed, the Empty
Flag (EF) will go high after tWEF and a valid read may then be initiated. When the FIFO
stack is empty, the internal read pointer is blocked from R, so that external changes to R
will have no effect on the empty FIFO stack.
First Load/Retransmit
(FL/RT)
This pin is a dual-purpose input. In the Depth Expansion Mode, this pin is connected to
ground to indicate that it is the first loaded (see Operating Modes). In the Single Device
Mode, this pin acts as the retransmit input. The Single Device Mode is initiated by con-
necting the Expansion In (XI) to ground.
The M67206H can be set to retransmit data when the Retransmit Enable Control (RT)
input is pulsed low. A retransmit operation will set the internal read point to the first loca-
tion and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be
in the high state during retransmit. The retransmit feature is intended for use when a
number of writes are equal to or less than the depth of the FIFO has occurred since the
last RS cycle. The retransmit feature is not compatible with the Depth Expansion Mode
and will affect the Half-Full Flag (HF), in accordance with the relative locations of the
read and write pointers.
Expansion In (XI)
The XI input is a dual-purpose pin. Expansion In (XI) is connected to GND to indicate an
operation in the single device mode. Expansion In (XI) is connected to Expansion Out
(XO) of the previous device in the Depth Expansion or Daisy Chain modes.
Full Flag (FF)
The Full Flag (FF) will go low, inhibiting further write operations when the write pointer is
one location less than the read pointer, indicating that the device is full. If the read
pointer is not moved after Reset (RS), the Full Flag (FF) will go low after 16384 writes.
Empty Flag (EF)
The Empty Flag (EF) will go low, inhibiting further read operations when the read pointer
is equal to the write pointer, indicating that the device is empty.


Similar Part No. - SMCP-67206HV-15SCC

ManufacturerPart #DatasheetDescription
logo
ATMEL Corporation
SMCP-672061HV-15SCC ATMEL-SMCP-672061HV-15SCC Datasheet
2Mb / 20P
   Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO with Programmable Flag
SMCP-672061HV-30SCC ATMEL-SMCP-672061HV-30SCC Datasheet
2Mb / 20P
   Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO with Programmable Flag
More results

Similar Description - SMCP-67206HV-15SCC

ManufacturerPart #DatasheetDescription
logo
ATMEL Corporation
M67204H ATMEL-M67204H Datasheet
1Mb / 20P
   Rad. Tolerant High Speed 4 Kb x 9 Parallel FIFO
M672061H ATMEL-M672061H Datasheet
2Mb / 20P
   Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO with Programmable Flag
M67025E ATMEL-M67025E Datasheet
531Kb / 27P
   Rad. Tolerant High Speed 8 Kb x 16 Dual Port RAM
M67025E ATMEL-M67025E_07 Datasheet
693Kb / 27P
   Rad. Tolerant High Speed 8 Kb x 16 Dual Port RAM
logo
Maxwell Technologies
7206F MAXWELL-7206F Datasheet
208Kb / 15P
   High-Speed Epi-CMOS (16K x 9-Bit) Parallel FIFO
logo
Integrated Device Techn...
IDT72103 IDT-IDT72103 Datasheet
314Kb / 31P
   CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9
logo
Sharp Corporation
LH5493 SHARP-LH5493 Datasheet
839Kb / 16P
   4K x 9 Parallel-to Serial FIFO
logo
Texas Instruments
UC1825A-DIE TI-UC1825A-DIE_15 Datasheet
153Kb / 5P
[Old version datasheet]   RAD-TOLERANT, HIGH-SPEED PWM CONTROLLER
logo
Integrated Device Techn...
IDT72131 IDT-IDT72131 Datasheet
126Kb / 13P
   CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 4096 X 9
logo
Texas Instruments
UC1825-DIE TI-UC1825-DIE_15 Datasheet
120Kb / 5P
[Old version datasheet]   RAD-TOLERANT, HIGH-SPEED PWM CONTROLLER
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com