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TSC21020F-20MB-E Datasheet(PDF) 10 Page - ATMEL Corporation |
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TSC21020F-20MB-E Datasheet(HTML) 10 Page - ATMEL Corporation |
10 / 50 page 10 TSC21020F 4153H–AERO–04/07 program and data memory interfaces in a high impedance state. In addition, three-state controls (DTMS and PMTS) allow an external device to place either the program or data memory interface in a high impedance state without affecting the other interface and without halting the TSC21020F unless it requires a memory access from the affected interface. The three-state controls make it easy for an external cache controller to hold the TSC21020F off the bus while it updates an external cache memory. JTAG Test and Emulation Support The TSC21020F implements the boundary scan testing provisions specified by IEEE Standard 1149.1 of the Joint Testing Action Group (JTAG). The TSC21020F's test access port and On-chip JTAG circuitry is fully compliant with the IEEE 1149.1 specifi- cation. The test access port enables boundary scan testing of circuitry connected to the TSC21020F's I/O pins. The TSC21020F also implements On-chip emulation through the JTAG test access port. The processor's eight sets of breakpoint range registers enable program execution at full speed until reaching a desired breakpoint address range. The processor can then halt and allow reading/writing of all the processor's internal registers and external mem- ories through the JTAG port. |
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