PACKAGE INFORMATION – PIN DIAGRAM

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

VDDP0

OE0

MUX

VSS

IN+

IN-

VSS

OE1

VDD

VDDP

OUT+

OUT-

VDDP

VSS

OUT0+

OUT0-

VDDP0

VSS

IN0+

IN0-

VDDP1

OUT1+

OUT1-

VDDP1

IN1+

IN1-

MUX0

MUX1

SN65LVCP15

(TOP VIEW)

MOISTURE SENSITIVITY LEVEL

SN65LVCP15

PIN FUNCTIONS

PIN

TYPE

LEVEL

DESCRIPTION

NO.

NAME

5, 6

IN+, IN–

24, 23

IN0+, IN0–

I

PECL

18, 17

IN1+, IN1–

11, 12

OUT+, OUT–

28, 27

OUT0+, OUT0–

O

PECL

Differential high-speed serial outputs

21, 20

OUT1+, OUT1–

2

OE0

OE0/OE1 enables OUT0/OUT1 when HIGH. When LOW, OUTx is powered down and both

I

TTL

OUTx+ and OUTx– float HIGH.

8

OE1

3

MUX

I

TTL

Determines source of OUT. Selects either IN0 (LOW) or IN1 (HIGH).

15

MUX1

I

TTL

Determines source of OUT1. Selects either IN (HIGH) or IN0 (LOW).

16

MUX0

I

TTL

Determines source of OUT0. Selects either IN (LOW) or IN1 (HIGH).

9

VDD

Pwr

3.3 V power supply for digital logic

10, 13

VDDP

High-speed output power supply: 3.3 V supply for PECL drivers. VDDP0 is for OUT0, VDDP

1, 26

VDDP0

Pwr

is for OUT, and VDDP1 is for OUT1.

19, 22

VDDP1

4, 7

VSS

Pwr

Ground

14, 25

This device is rated moisture sensitivity level 3 or better as specified in the joint IPC and JEDEC standard

IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standards.

4

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