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CMS6416LAG Datasheet(PDF) 3 Page - FIDELIX |
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CMS6416LAG Datasheet(HTML) 3 Page - FIDELIX |
3 / 46 page Rev1.3, Nov. 2005 CMS6416LAx-75xx Features - Functionality - Standard SDRAM Functionality - Programmable burst lengths : 1, 2, 4, 8, or full page - JEDEC Compatibility - Low Power Features - Low voltage power supply : 2.5V/3.0V - Auto TCSR(Temperature Compensated Self Refresh) - Partial Array Self Refresh power-saving mode - Deep Power Down Mode - Driver Strength Control - Operating Temperature Ranges: - Special (-10℃ to +60℃) - Commercial (0℃ to +70℃) - Extended (-25℃ to +85℃) - Industrial (-40℃ to +85℃) - LVCMOS Compatible IO Interface - 54ball FBGA with 0.8mm ball pitch - CMS6416LAF : Normal - CMS6416LAG : Pb-Free - CMS6416LAH : Pb-Free & Halogen Free Functional Description The CMS6416LAx-xxxx family is high-performance CMOS Dynamic RAMs (DRAM) organized as 4M x 16. These devices feature advanced circuit design to provide ultra-low active current and extremely low standby current.This is ideal for providing More Battery Life in portable applications such as wireless handsets. The device is compatible with the JEDEC standard LP-SDRAM specifications. Selection Guide 20ns 20ns 7.5ns 100MHz 18ns 18ns 6ns 133MHz 1.65-VDD 2.3-3.3V CMS6416LAx-75xx t RCD CL=2 Access Time(t AC) CL=3 V DDQ V DD t RP Frequency Voltage Device Column Decoder Column Decoder Column Decoder Bank 0 Row Addr Latch/ Decoder Bank 3 Bank 2 Bank 1 Bank 0 Row Addr Latch/ Decoder Bank 0 Memory Array 4Kx4K Sense Amp Row Add Mux Write Drivers DQM Mask READ DATA LATCH Data Output Reg Column Address Latch Bank Control Logic Refresh Counter Addr Reg Data Output Reg LDQM - UDQM DQ0 - DQ15 Column Decoder Enhanced Mode Reg Mode Reg Control Logic CKE CLK /CS /WE /CAS /RAS A0-A11 BA0-BA1 Logic Block Diagram |
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