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TL28L92 Datasheet(PDF) 40 Page - Texas Instruments |
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TL28L92 Datasheet(HTML) 40 Page - Texas Instruments |
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40 / 61 page  3.3.10 Input Port Change Register (IPCR) 3.3.11 Interrupt Status Register (ISR) TL28L92 3.3-V/5-V Dual Universal Asynchronous Receiver/Transmitter SLLS890A – AUGUST 2008 – REVISED OCTOBER 2008 www.ti.com Table 3-51. ACR[6:4] Field Definition(1) ACR[6:4] MODE CLOCK SOURCE 000 Counter External IP2 001 Counter TxCA – 1 × clock of channel A transmitter 010 Counter TxCB – 1 × clock of channel B transmitter 011 Counter Crystal or external clock (X1/CLK) divided by 16 100 Timer External (IP2) 101 Timer External (IP2) divided by 16 110 Timer Crystal or external clock (X1/CLK) 111 Timer Crystal or external clock (X1/CLK) divided by 16 (1) The timer mode generates a square wave. Table 3-52. Input Port Change Register (IPCR) (Address 0x4) Bit Allocation 7 6 5 4 3 2 1 0 ΔIP3 ΔIP2 ΔIP1 ΔIP0 state of IP3 state of IP2 state of IP1 state of IP0 Table 3-53. Input Port Change Register (IPCR) (Address 0x4) Bit Description BIT(S) SYMBOL DESCRIPTION 7 to 4 – IP3, IP2, IP1 and IP0 change of state. 0 = no change 1 = change These bits are set when a change of state, as defined in Section 2.2.9, occurs at the respective input pins. They are cleared when the IPCR is read by the CPU. A read of the IPCR also clears ISR[7], the input change bit in the interrupt status register. The setting of these bits can be programmed to generate an interrupt to the CPU. 3 to 0 – IP3, IP2, IP1 and IP0 state. 0 = LOW 1 = HIGH These bits provide the current state of the respective inputs. The information is unlatched and reflects the state of the input pins at the time the IPCR is read. This register provides the status of all potential interrupt sources. The contents of this register are masked by the Interrupt Mask Register (IMR). If a bit in the ISR is a logic 1 and the corresponding bit in the IMR is also a logic 1, the INTRN output will be asserted (LOW). If the corresponding bit in the IMR is a zero, the state of the bit in the ISR has no effect on the INTRN output. Note that the IMR does not mask the reading of the ISR. The true status will be provided regardless of the contents of the IMR. The contents of this register are initialized to 0x0 when the DUART is reset. Table 3-54. Interrupt Status Register (ISR) (Address 0x5) Bit Allocation 7 6 5 4 3 2 1 0 change input change break RxRDYB TxRDYB counter ready change break A RxRDYA TxRDYA port B Programming 40 Submit Documentation Feedback |
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