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TL28L92 Datasheet(PDF) 21 Page - Texas Instruments |
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TL28L92 Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 61 page  2.3.6 Receiver Reset and Disable 2.3.7 Watchdog 2.3.8 Receiver Time-Out Mode TL28L92 3.3-V/5-V Dual Universal Asynchronous Receiver/Transmitter www.ti.com SLLS890A – AUGUST 2008 – REVISED OCTOBER 2008 If the FIFO is full when a new character is received, that character is held in the receive shift register until a FIFO position is available. If an additional character is received while this state exits, the contents of the FIFO are not affected; the character previously in the shift register is lost and the overrun error status bit (SR[4]) will be set upon receipt of the start bit of the new (overrunning) character. The receiver can control the deactivation of RTS. If programmed to operate in this mode, the RTSN output will be negated when a valid start bit was received and the FIFO is full. When a FIFO position becomes available, the RTSN output will be reasserted (set LOW) automatically. This feature can be used to prevent an overrun, in the receiver, by connecting the RTSN output to the CTSN input of the transmitting device. If the receiver is disabled, the FIFO characters can be read. However, no additional characters can be received until the receiver is enabled again. If the receiver is reset, the FIFO and all of the receiver status, and the corresponding output ports and interrupt are reset. No additional characters can be received until the receiver is enabled again. Receiver disable stops the receiver immediately. Data being assembled in the receiver shift register is lost. Data and status in the FIFO is preserved and may be read. A re-enable of the receiver after a disable will cause the receiver to begin assembling characters at the next start bit detected. A receiver reset will discard the present shift register date, reset the receiver ready bit (RxRDY), clear the status of the byte at the top of the FIFO and realign the FIFO read/write pointers. A watchdog timer is associated with each receiver. Its interrupt is enabled by MR0[7]. The purpose of this timer is to alert the control processor that characters are in the Rx FIFO which have not been read. This situation may occur at the end of a transmission when the last few characters received are not sufficient to cause an interrupt. This counter times out after 64 bit times. It is reset each time a character is transferred from the receiver shift register to the Rx FIFO or a read of the Rx FIFO is executed. In addition to the watchdog timer described in the receiver section, the counter/timer may be used for a similar function. Its programmability, of course, allows much greater precision of time-out intervals. The time-out mode uses the received data stream to control the counter. Each time a received character is transferred from the shift register to the Rx FIFO, the counter is restarted. If a new character is not received before the counter reaches zero count, the counter ready bit is set, and an interrupt can be generated. This mode can be used to indicate when data has been left in the Rx FIFO for more than the programmed time limit. Otherwise, if the receiver has been programmed to interrupt the CPU when the receive FIFO is full, and the message ends before the FIFO is full, the CPU may not know there is data left in the FIFO. The CTU and CTL value would be programmed for just over one character time, so that the CPU would be interrupted as soon as it has stopped receiving continuous data. This mode can also be used to indicate when the serial line has been marking for longer than the programmed time limit. In this case, the CPU has read all of the characters from the FIFO, but the last character received has started the count. If there is no new data during the programmed time interval, the counter ready bit will get set, and an interrupt can be generated. The time-out mode is enabled by writing the appropriate command to the command register. Writing 0xA to CRA or CRB will invoke the time-out mode for that channel. Writing 0xC to CRA or CRB will disable the time-out mode. The time-out mode should only be used by one channel at once, since it uses the C/T. If, however, the time-out mode is enabled from both receivers, the time-out will occur only when both receivers have stopped receiving data for the time-out period. CTU and CTL must be loaded with a value greater than the normal receive character period. The time-out mode disables the regular start counter or stop counter commands and puts the C/T into counter mode under the control of the received data Submit Documentation Feedback Functional Description 21 |
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