TL28L92 datasheet(25/61 Pages) TI

Part #	TL28L92

Description	3.3-V/5-V Dual Universal Asynchronous Receiver/Transmitter

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Manufacturer	TI [Texas Instruments]

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TL28L92

3.3-V/5-V Dual Universal Asynchronous Receiver/Transmitter

www.ti.com

SLLS890A – AUGUST 2008 – REVISED OCTOBER 2008

Table 3-9. Channel Status Register (SR)

7

6

5

4

3

2

1

0

received

framing error

parity error

overrun error

TxEMT

TxRDY

RxFULL

RxRDY

break

Table 3-10. Interrupt Mask Register (Enables Interrupts) (IMR)

7

6

5

4

3

2

1

0

change input

change break B

RxRDYB

TxRDTYB

counter ready

change break A

RxRDYA

TxRDYA

port

Table 3-11. Interrupt Status Register (ISR)

7

6

5

4

3

2

1

0

input port

RxRDYB

RxRDYA

change break B

TxRDTYB

counter ready

change break A

TxRDYA

change

FFULLB

FFULLA

Table 3-12. Counter/Timer Preset Register, Upper (CTPU)

7

6

5

4

3

2

1

0

8 MSB of the BRG timer divisor

Table 3-13. Counter/Timer Preset Register, Lower (Enables Interrupts) (CTPL)

7

6

5

4

3

2

1

0

8 LSB of the BRG timer divisor

Table 3-14. Auxiliary Control Register and Change of State Control (ACR)

7

6

5

4

3

2

1

0

counter/timer mode and clock source select

enable IP3

enable IP2

enable IP1

enable IP0

BRG set select

(see Table 3-51)

COS interrupt

Table 3-15. Input Port Change Register (IPCR)

7

6

5

4

3

2

1

0

delta IP3

delta IP2

delta IP1

delta IP0

state of IP3

state of IP2

state of IP1

state of IP0

Table 3-16. Input Port Register (IPR)

7

6

5

4

3

2

1

0

state of IP7

state of IP6

state of IP5

state of IP4

state of IP3

state of IP2

state of IP1

state of IP0

Table 3-17. Set Output Port Bits Register (SOPR)

7

6

5

4

3

2

1

0

set OP7

set OP6

set OP5

set OP4

set OP3

set OP2

set OP1

set OP0

Table 3-18. Reset Output Port Bits Register (ROPR)

7

6

5

4

3

2

1

0

reset OP7

reset OP6

reset OP5

reset OP4

reset OP3

reset OP2

reset OP1

reset OP0

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