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TLC5926IPWPRG4 Datasheet(PDF) 10 Page - Texas Instruments |
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TLC5926IPWPRG4 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 29 page Switching Characteristics TLC5926, TLC5927 SLVS677 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com VDD = 3 V, TJ = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH1 Low-to-high propagation delay time, CLK to OUTn 35 65 105 ns tPLH2 Low-to-high propagation delay time, LE(ED1) to OUTn 35 65 105 ns tPLH3 Low-to-high propagation delay time, OE(ED2) to OUTn 35 65 105 ns tPLH4 Low-to-high propagation delay time, CLK to SDO 20 45 ns tPHL1 High-to-low propagation delay time, CLK to OUTn 200 300 470 ns tPHL2 High-to-low propagation delay time, LE(ED1) to OUTn 200 300 470 ns tPHL3 High-to-low propagation delay time, OE(ED2) to OUTn 200 300 470 ns tPHL4 High-to-low propagation delay time, CLK to SDO 20 40 ns tw(CLK) Pulse duration, CLK 20 ns VIH = VDD, VIL = GND, tw(L) Pulse duration LE(ED1) 20 ns Rext = 360 Ω, VL = 4 V, tw(OE) Pulse duration, OE(ED2) 1000 ns RL = 44 Ω, CL = 70 pF, tw(ED2) Pulse duration, OE(ED2) in Error Detection mode 2 µs CG = 0.992 th(ED1,ED2) Hold time, LE(ED1), and OE(ED2) 10 ns th(D) Hold time, SDI 5 ns tsu(D,ED1,ED2) Setup time, SDI, LE(ED1), and OE(ED2) 7 ns th(L) Hold time, LE(ED1), Normal mode 18 ns tsu(L) Setup time, LE(ED1), Normal mode 18 ns tr Rise time, CLK(1) 500 ns tf Fall time, CLK(1) 500 ns tor Rise time, outputs (off) 245 ns tof Rise time, outputs (on) 600 ns fCLK Clock frequency Cascade operation 30 MHz (1) If the devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer between two cascaded devices. 10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5926 TLC5927 |
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