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HCPL-7840 Datasheet(PDF) 11 Page - AVAGO TECHNOLOGIES LIMITED |
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HCPL-7840 Datasheet(HTML) 11 Page - AVAGO TECHNOLOGIES LIMITED |
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11 / 19 page  11 Figure 3. Input offset vs. supply. Figure 4. Gain vs. temperature. Figure 1. Input offset voltage test circuit. Figure 2. Input offset voltage vs. temperature. Figure 5. Gain and nonlinearity test circuit. HCPL-7840 fig 1 0.1 µF VDD2 VOUT 8 7 6 1 3 HCPL-7840 5 2 4 0.1 µF 10 K 10 K VDD1 +15 V 0.1 µF 0.1 µF -15 V + – AD624CD GAIN = 100 0.47 µF 0.47 µF HCPL-7840 fig 5 0.1 µF VDD2 8 7 6 1 3 HCPL-7840 5 2 4 0.01 µF 10 K 10 K +15 V 0.1 µF 0.1 µF -15 V + – AD624CD GAIN = 4 0.47 µF 0.47 µF VDD1 13.2 404 VIN VOUT +15 V 0.1 µF 0.1 µF -15 V + – AD624CD GAIN = 10 10 K 0.47 µF 0.1 µF TA – TEMPERATURE – °C 0.6 0.5 0.3 -25 HCPL-7840 fig 2 0.8 35 95 0.2 0.7 -55 125 0.4 5 65 VDD – SUPPLY VOLTAGE – V 0.37 0.36 HCPL-7840 fig 3 0.39 4.75 5.0 0.33 vs. VDD1 4.5 5.5 5.25 vs. VDD2 0.34 0.38 0.35 TA – TEMPERATURE – °C 8.025 8.02 8.015 -35 HCPL-7840 fig 4 8.035 25 85 8.01 8.03 -55 125 5 45 105 -15 65 |
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