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SCG2010 Datasheet(PDF) 2 Page - Connor-Winfield Corporation

Part # SCG2010
Description  Synchronous Clock Generators
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Manufacturer  CONNOR-WINFIELD [Connor-Winfield Corporation]
Direct Link  http://www.conwin.com
Logo CONNOR-WINFIELD - Connor-Winfield Corporation

SCG2010 Datasheet(HTML) 2 Page - Connor-Winfield Corporation

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Data Sheet #: SG035
Page 2 of 20
Rev: 00
Date: 08/23/04
© Copyright 2004 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Functional Block Diagram
Figure 1
ALARM
DETECTION
Reference Input
(Pin 8)
DIVIDER
DPFD
ANALOG
FILTER
DIVIDER
FREE RUN
CONTROL
Free Run Enable
(Pin 5)
Input Freq. Select A
(Pin 14)
LOL Alarm Output
(Pin 7)
VCXO
LOR Alarm Output
(Pin 6)
Oscillator Output
(Pin 9)
Optional Oscillator Output
(Pin 1)
Reference Output
(Pin 1)
(Not available on
models with optional
oscillator output)
Input Freq. Select B
(Pin 13)
Tri-State Enable
(Pin 10)
also enter a Free Run state which will guarantee a 20 ppm
accurate output. Additionally the Free Run mode may be
entered manually by asserting a high signal to the Free
Run Enable pin. The outputs, except the oscillator output,
may be put into the tri-state high impedance condition for
external testing purposes by asserting a high signal to the
Tri-State Enable pin.
The SCG2000 Series are 3.3 Volt components that
typically draw less than 100 mA. All models have an
acquisition time of approximately 1.0 second and can be
used in applications that require temperature rating of 0° -
70° C. All models have a 33
Ω resistor in series with the
oscillator output. The SCG2000 maximum package
dimensions are .78” x .83” x .35” on a six layer FR4 board
with surface mount pins. Parts are assembled using high
temperature solder to withstand surface mount reflow
process.
General Description
The SCG2000 Series provides high precision phase lock loop
frequency translation for the telecommunication applications.
The SCG2000 products generate a CMOS output from an
intrinsically low jitter, voltage controlled crystal oscillator. Most
models provide a jitter attenuated, internal reference that is
connected to a Reference Output pin.
SCG2000 Series is well suited for use in line cards, service
termination cards and similar functions to provide reliable
reference, phase locked, synchronization for TDM, PDH, SONET
and SDH network equipment . The SCG2000 Series provides a
low phase gain (<0.2dB), jitter filtered, wander following output
signal synchronized to a superior Stratum or peer input reference
signal.
The SCG2000 Series include the following features: Free
Run, Tri-state and alarm outputs for Loss-of-Reference, (LOR),
Loss-of-Lock, (LOL). During the LOR alarm, the SCG2000 will
Model Comparison Table
Table 1
Max
Model
Input
Duty
Reference Output
Oscillator Output
Notes
Ref Freq
Cycle
(Pin #1)
(Pin #9)
SCG2000
8-64 kHz
40/60
= Input Ref Freq.
1.544 MHz to 125.0 MHz
Basic Model
SCG2010
19.44 MHz
40/60
8 kHz
19.44 MHz
SCG2020
19.44 MHz
40/60
19.44 MHz
77.76 MHz
SCG2030
8-64 kHz
45/55
= Input Ref Freq.
1.544 MHz to 125.0 MHz
Tight Duty Cycle
SCG2050
8-64 kHz
40/60
19.44 MHz
77.76 MHz
SCG2070
19.44 MHz
40/60
51.84 MHz, 77.76 MHz
51.84 MHz, 77.76 MHz
Ref Output = Osc Output
*Features which differentiate a model from the base model (SCG2000) are highlighted in boldface color and in the notes column.


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