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EP2C8A15F324I8ES Datasheet(PDF) 43 Page - Altera Corporation |
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EP2C8A15F324I8ES Datasheet(HTML) 43 Page - Altera Corporation |
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43 / 168 page  Altera Corporation 2–31 February 2007 Cyclone II Device Handbook, Volume 1 Cyclone II Architecture Clock Modes Table 2–8 summarizes the different clock modes supported by the M4K memory. Table 2–9 shows which clock modes are supported by all M4K blocks when configured in the different memory modes. M4K Routing Interface The R4, C4, and direct link interconnects from adjacent LABs drive the M4K block local interconnect. The M4K blocks can communicate with LABs on either the left or right side through these row resources or with LAB columns on either the right or left with the column resources. Up to 16 direct link input connections to the M4K block are possible from the left adjacent LAB and another 16 possible from the right adjacent LAB. M4K block outputs can also connect to left and right LABs through each 16 direct link interconnects. Figure 2–17 shows the M4K block to logic array interface. Table 2–8. M4K Clock Modes Clock Mode Description Independent In this mode, a separate clock is available for each port (ports A and B). Clock A controls all registers on the port A side, while clock B controls all registers on the port B side. Input/output On each of the two ports, A or B, one clock controls all registers for inputs into the memory block: data input, wren, and address. The other clock controls the block’s data output registers. Read/write Up to two clocks are available in this mode. The write clock controls the block’s data inputs, wraddress, and wren. The read clock controls the data output, rdaddress, and rden. Single In this mode, a single clock, together with clock enable, is used to control all registers of the memory block. Asynchronous clear signals for the registers are not supported. Table 2–9. Cyclone II M4K Memory Clock Modes Clocking Modes True Dual-Port Mode Simple Dual-Port Mode Single-Port Mode Independent v Input/output vv v Read/write v Single clock vv v |
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