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EP2C8A15F324C6N Datasheet(PDF) 17 Page - Altera Corporation |
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EP2C8A15F324C6N Datasheet(HTML) 17 Page - Altera Corporation |
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17 / 168 page  Altera Corporation 2–5 February 2007 Cyclone II Device Handbook, Volume 1 Cyclone II Architecture Figure 2–3. LE in Normal Mode Arithmetic Mode The arithmetic mode is ideal for implementing adders, counters, accumulators, and comparators. An LE in arithmetic mode implements a 2-bit full adder and basic carry chain (see Figure 2–4). LEs in arithmetic mode can drive out registered and unregistered versions of the LUT output. Register feedback and register packing are supported when LEs are used in arithmetic mode. data1 Four-Input LUT data2 data3 cin (from cout of previous LE) data4 clock (LAB Wide) ena (LAB Wide) aclr (LAB Wide) CLRN D Q ENA sclear (LAB Wide) sload (LAB Wide) Register chain connection Register chain output Row, Column, and Direct Link Routing Row, Column, and Direct Link Routing Local routing Register Feedback Packed Register Input |
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