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EP2C8A8U324C7N Datasheet(PDF) 86 Page - Altera Corporation |
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EP2C8A8U324C7N Datasheet(HTML) 86 Page - Altera Corporation |
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86 / 168 page  4–4 Altera Corporation Cyclone II Device Handbook, Volume 1 February 2007 Hot-Socketing Feature Implementation in Cyclone II Devices Figure 4–1. Hot-Socketing Circuit Block Diagram for Cyclone II Devices The POR circuit monitors VCCINT voltage level and keeps I/O pins tri-stated until the device is in user mode. The weak pull-up resistor (R) from the I/O pin to VCCIO keeps the I/O pins from floating. The voltage tolerance control circuit permits the I/O pins to be driven by 3.3 V before VCCIO and/or VCCINT are powered, and it prevents the I/O pins from driving out when the device is not in user mode. f For more information, see the DC Characteristics & Timing Specifications chapter in Volume 1 of the Cyclone II Device Handbook for the value of the internal weak pull-up resistors. Figure 4–2 shows a transistor level cross section of the Cyclone II device I/O buffers. This design ensures that the output buffers do not drive when VCCIO is powered before VCCINT or if the I/O pad voltage is higher than VCCIO. This also applies for sudden voltage spikes during hot socketing. The VPAD leakage current charges the voltage tolerance control circuit capacitance. Output Enable Output Hot Socket Output Pre-Driver Voltage Tolerance Control Power-On Reset Monitor Weak Pull-Up Resistor PAD Input Buffer to Logic Array R |
Similar Part No. - EP2C8A8U324C7N |
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