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EP2C8A8U324I7N Datasheet(PDF) 41 Page - Altera Corporation |
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EP2C8A8U324I7N Datasheet(HTML) 41 Page - Altera Corporation |
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41 / 168 page  Altera Corporation 2–29 February 2007 Cyclone II Device Handbook, Volume 1 Cyclone II Architecture Table 2–6 summarizes the features supported by the M4K memory. Table 2–6. M4K Memory Features Feature Description Maximum performance (1) 250 MHz Total RAM bits per M4K block (including parity bits) 4,608 Configurations supported 4K × 1 2K × 2 1K × 4 512 × 8 512 × 9 256 × 16 256 × 18 128 × 32 (not available in true dual-port mode) 128 × 36 (not available in true dual-port mode) Parity bits One parity bit for each byte. The parity bit, along with internal user logic, can implement parity checking for error detection to ensure data integrity. Byte enable M4K blocks support byte writes when the write port has a data width of 1, 2, 4, 8, 9, 16, 18, 32, or 36 bits. The byte enables allow the input data to be masked so the device can write to specific bytes. The unwritten bytes retain the previous written value. Packed mode Two single-port memory blocks can be packed into a single M4K block if each of the two independent block sizes are equal to or less than half of the M4K block size, and each of the single-port memory blocks is configured in single-clock mode. Address clock enable M4K blocks support address clock enable, which is used to hold the previous address value for as long as the signal is enabled. This feature is useful in handling misses in cache applications. Memory initialization file (.mif) When configured as RAM or ROM, you can use an initialization file to pre-load the memory contents. Power-up condition Outputs cleared Register clears Output registers only Same-port read-during-write New data available at positive clock edge Mixed-port read-during-write Old data available at positive clock edge Note to Table 2–6: (1) Maximum performance information is preliminary until device characterization. |
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