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TC28C43 Datasheet(PDF) 5 Page - TelCom Semiconductor, Inc |
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TC28C43 Datasheet(HTML) 5 Page - TelCom Semiconductor, Inc |
5 / 7 page 4-97 TELCOM SEMICONDUCTOR, INC. 7 6 5 4 3 1 2 8 TC18C43 TC28C43 TC38C43 BiCMOS CURRENT MODE PWM CONTROLLERS Dead Time The value of RT has an effect on the discharge rate but the primary consideration is the value of CT. The time required to discharge the capacitor is approximately 1000 CT. Undervoltage Lockout Range The TCx8C43 PWM Controller is used where wide ranges of input voltage is not required. The range from starting Vin voltage threshold to under voltage threshold is approximately 9.5% of the starting voltage. The typical start- up voltage is 8.4V and dropout voltage is 7.6V. This range is used most in DC-to-DC converter applications. Duty Cycle Limit The TCx8C43 PWM Controller has a duty cycle limit maximum of 99%. The oscillator is running at the same frequency as the output. Current is sensed through voltage drop across resistor RS. A small RC filter may be required to suppress switching transient. This voltage enters PWM Controller at ISENSE, pin 5. A voltage of 0.4 V is added before this is fed into PWM Comparator (+) input. The PWM Comparator (–) input senses the voltage feedback error amp output with a limit buffer that limits this voltage to 1.4V maximum. This limit buffer limits the peak current across RS to a maximum of 0.95V. In normal operation, the error amplifier controls the current limit threshold. Shutdown can be accomplished by either pulling ISENSE above 1 volt or pulling CMPTR, pin 1 to GND. This will set the PWM latch so that the output will remain low until the next clock pulse after the shutdown condition is removed. SHUTDOWN METHODS TCx8C43 VON = 8.4V VOFF = 7.6V IS 7.6V 8.4 V 1mA 170 µA VDD VIN TCx8C43 ERROR AMP + – LIMIT BUFFER + – 1.4V 2R R GND + – C R ISENSE 5 0.4V PWM COMPARATOR 9 RS PEAK CURRENT (IS) FORMULA: IS = 0.95V RS CURRENT SENSE CIRCUIT ISENSE 5 TCx38C43 VREF SHUTDOWN 14 TO CURRENT SENSE RESISTOR 5k 5.1k 9 TCx38C43 SHUTDOWN ANALOG GND CMPTR 1 BENCH TEST OPERATIONAL SIMULATION The timing ramp (RT/CT) is buffered by the emitter fullpower and fed back to the ISENSE input. This ramp simulates the dI/dT current ramp which would flow through the primary of the transformer. The output voltage of the power supply is simulated by feeding some of the reference voltage into VFB. The combination of the two levels deter- mined the operating characteristics of the current mode controller. UNDERVOLTAGE LOCKOUT RANGE |
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