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TELCOM SEMICONDUCTOR, INC.

TC520A

SERIAL INTERFACE ADAPTER FOR

TC500 A/D CONVERTER FAMILY

PIN DESCRIPTIONS (Cont.)

Pin No.

Pin No.

14-Pin PDIP 16-Pin SOIC

Package

Package

Symbol

Description

11

13

Input, logic level. Serial port input pin. The TC5xx A/D converter integration

time (TINT) and Autozero time (TAZ) values are determined by the LOAD

VALUE byte clocked into this pin. This initialization must take place at power

up, and can be rewritten (or modified and rewritten) at any time. The LOAD

12

14

LOAD

Input, active low; level and edge triggered. The LOAD VALUE is clocked into

the 8 bit shift register on board the TC520A while LOAD is held low. The LOAD

VALUE is then transferred into the TC520A internal timebase counter (and

becomes effective) when LOAD is returned high. If so desired, LOAD can be

momentarily pulsed low (eliminating the need to clock a LOAD VALUE into

13

15

DV

Output, active low. DV is brought any time the TC520A is in the AZ phase of

conversion. This occurs when either the TC520A initiates a normal AZ phase

by setting A, B, equal to 01; or when CE is pulled high (which overrides the

normal A, B sequencing and forces an AZ state). DV is returned high when the

TC520A exits AZ.

14

16

CE

Input, active low, level triggered. Conversion will be continuously performed as

long as CE remains low. Pulling CE high causes the conversion process to be

halted, and forces the TC520 into the AZ mode for as long as CE remains

high. CE should be taken high whenever it is necessary to momentarily

suspend conversion (for example: to change the address lines of an input

multiplexer). CE should be pulled high only when the TC520A enters an AZ

phase (i.e. when DV is low). This is necessary to avoid excessively long

integrator discharge times which could result in erroneous conversion. This pin

should be grounded if unused. It should be left floating if a 0.01

µF RESET

capacitor is connected to it (see

Applications section).

TC520A Timing

The TC520A consists of a serial port and state machine.

The state machine provides control timing to both the TC5xx

A/D converter connected to the TC520A, as well as sequen-

tial timing for TC520A internal operation. All timing is de-

frequency source can be either an externally-provided clock

signal, or external crystal. If an external clock is used, it must

floating.

If a crystal is used, it must be connected between the

quency is internally divided by 4 and the resulting clock

(SYSCLK) controls all timing functions.

TC5xx A/D Converter Control Signals

The TC520A control outputs (A, B) and control input

(CMPTR) connect directly to the corresponding pins of the

TC5xx A/D converter. A conversion is consummated when

A, B have been sequenced through the required 4 phases of

conversion: Auto Zero (AZ), Integrate (INT), De-integrate

phase compensates for offset errors in the TC5xx A/D

converter. The integrate phase connects the voltage to be

converted to the TC5xx A/D converter input (resulting in an

integrator output dv/dt directly proportional to the magnitude

of the applied input voltage). Actual A/D conversion (count-

when the integrator output crosses 0V. The integrator output

is then forced to 0V during the IZ phase and the converter is

ready for another cycle. Please see the TC500/500A/510/

514 data sheet for a complete description of these phases.

The number of SYSCLK periods (counts) for the AZ and

INT phases is determined by the LOAD VALUE. The LOAD

VALUE is a single byte that must be loaded into the most

significant byte of 16 bit counter on-board the TC520A during

initialization. The lower byte of this counter is pre-loaded to

The LOAD VALUE (upper 8 bits of the counter) can be

programmed over a range of 0FFH to 00H (corresponding to