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LT1970CFE Datasheet(PDF) 11 Page - Linear Technology |
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LT1970CFE Datasheet(HTML) 11 Page - Linear Technology |
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11 / 24 page  11 LT1970 1970fb APPLICATIO S I FOR ATIO its very high transconductance, takes control from the input stage, GM1. The output current is regulated to a value of IOUT = VSENSE/RSENSE = (VCSRC or VCSNK)/(10 • RSENSE). The time required for the current limit amplifiers to take control of the output is typically 4 µs. Linear operation of the current limit sense amplifier oc- curs with the inputs SENSE+ and SENSE– ranging be- tween VCC – 1.5V and VEE + 1.5V. Most applications will connect pins SENSE+ and OUT together, with the load on the opposite side of the external sense resistor and pin SENSE–. Feedback to the inverting input of GM1 should be connected from SENSE– to – IN. Ground side sensing of load current may be employed by connecting the load between pins OUT and SENSE+. Pin SENSE– would be connected to ground in this instance. Load current would be regulated in exactly the same way as the conventional connection. However, voltage mode accuracy would be degraded in this case due to the voltage across RSENSE. Creative applications are possible where pins SENSE+ and SENSE– monitor a parameter other than load current. The operating principle that at most one of the current limit stages may be active at one time, and that when active, the current limit stages take control of the output from GM1, can be used for many different signals. Current Limit Threshold Control Buffers Input pins VCSNK and VCSRC are used to set the response thresholds of current limit amplifiers “ISINK” and “ISRC”. Each of these inputs may be independently driven by a voltage of 0V to 5V above the COMMON reference pin. The 0V to 5V input voltage is attenuated by a factor of 10 and applied as an offset to the appropriate current limit ampli- fier. AC signals may be applied to these pins. The AC bandwidth from a VC pin to the output is typically 2MHz. For proper operation of the LT1970, these control inputs cannot be left floating. For low VCC supply applications it is important to keep the maximum input control voltages, VCSRC and VCSNK, at least 2.5V below the VCC potential. This ensures linear control of the current limit threshold. Reducing the current limit sense resistor value allows high output current from a smaller control voltage which may be necessary if the VCC supply is only 5V. The transfer function from VC to the associated VOS is linear from about 0.1V to 5V in, or 10mV to 500mV at the current limit amplifier inputs. An intentional nonlinearity is built into the transfer functions at low levels. This non- linearity insures that both the sink and source limit ampli- fiers cannot become active simultaneously. Simultaneous activation of the limit amplifiers could result in uncon- trolled outputs. As shown in the Typical Performance Characteristics curves, the control inputs have a “hockey stick” shape, to keep the minimum limit threshold at 4mV for each limit amplifier. Figure 1 illustrates an interesting use of the current sense input pins. Here the current limit control amplifiers are used to produce a symmetrically limited output voltage swing. Instead of monitoring the output current, the output voltage is divided down by a factor of 20 and applied to the SENSE+ input, with the SENSE– input grounded. When the threshold voltage between SENSE+ and SENSE– (VCLAMP/10) is reached, the current limit stage takes control of the output and clamps it a level of ±2 • VCLAMP. With control inputs VCSRC and VCSNK tied together, a single polarity input voltage sets the same + and – output limit voltage for symmetrical limiting. In this circuit the output will current limit at the built-in fail-safe level of typically 800mA. VCSRC COMMON VEE VCSNK V– FILTER V+ 12V EN VCC ISNK ISRC SENSE– SENSE+ TSD OUT +IN R3 3k 80mV TO 10V –80mV TO –10V ±CLAMP REACHED OUTPUT CLAMPS AT 2 × VCLAMP VCLAMP OV TO 5V VIN LT1970 –12V –IN R1 21.5k RL 1970 F01 R2 1.13k RF RG Figure 1. Symmetrical Output Voltage Limiting |
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