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TCM809LENB Datasheet(PDF) 3 Page - TelCom Semiconductor, Inc

Part # TCM809LENB
Description  3-PIN UP RESET MONITORS
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Manufacturer  TELCOM [TelCom Semiconductor, Inc]
Direct Link  http://www.telcom-semi.com
Logo TELCOM - TelCom Semiconductor, Inc

TCM809LENB Datasheet(HTML) 3 Page - TelCom Semiconductor, Inc

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TELCOM SEMICONDUCTOR, INC.
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PRELIMINARY INFORMATION
TCM809
TCM810
3-PIN
µP RESET MONITORS
valid to VCC = 0V, a pull-down resistor must be connected
from RESET to ground to discharge stray capacitances and
hold the output low (Figure 2). This resistor value, though
not critical, should be chosen such that it does not apprecia-
bly load RESET under normal operation (100k
Ω will be
suitable for most applications). Similarly, a pull-up resistor to
VCC is required for the TCM810 to ensure a valid high
RESET for VCC below 1.0V.
Processors With Bidirectional I/O Pins
Some
µP's (such as Motorola 68HC11) have bidirec-
tional reset pins. Depending on the current drive capability
of the processor pin, an indeterminate logic level may result
if there is a logic conflict. This can be avoided by adding a
4.7k resistor in series with the output of the TCM809/810
(Figure 3). If there are other components in the system
which require a reset signal, they should be buffered so as
not to load the reset line. If the other components are
required to follow the reset I/O of the
µP, the buffer should
be connected as shown with the solid line.
APPLICATIONS INFORMATION
VCC Transient Rejection
The TCM809/810 provides accurate VCC monitoring
and reset timing during power-up, power-down, and brown-
out/sag conditions, and rejects negative-going transients
(glitches) on the power supply line. Figure 1 shows the
maximum transient duration vs. maximum negative excur-
sion (overdrive) for glitch rejection. Any combination of
duration and overdrive which lies under the curve will not
generate a reset signal. Combinations above the curve are
detected as a brownout or power-down. Transient immunity
can be improved by adding a capacitor in close proximity to
the VCC pin of the TCM809/810.
RESET Signal Integrity During Power-Down
The TCM809 RESET output is valid to VCC = 1.0V.
Below this voltage the output becomes an "open circuit" and
does not sink current. This means CMOS logic inputs to the
µP will be floating at an undetermined voltage. Most digital
systems are completely shutdown well above this voltage.
However, in situations where RESET must be maintained
Figure 2. Ensuring RESET Valid to VCC = 0V
Figure 1. Maximum Transient Duration vs.
Overdrive for Glitch Rejection at 25
°C
Figure 3. Interfacing to Bidirectional Reset I/O
RESET COMPARATOR OVERDRIVE,
(VTH - VCC (mV)
400
240
160
320
80
0
1
10
100
1000
TA = +25°C
VTH
Duration
Overdrive
VCC
TCM8xxLM
TCM8xxR/S/T
TCM809
VCC
VCC
R1
100k
RESET
GND
TCM809
VCC
RESET
GND
RESET
GND
BUFFERED RESET
TO OTHER SYSTEM
COMPONENTS
BUFFER
µP
4.7k
VCC
VCC


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