LT5524 datasheet(4/16 Pages) LINER

Part #	LT5524

Description	Low Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain

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Manufacturer	LINER [Linear Technology]

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4

LT5524

5524f

VCC = 5V, VCCO = 5V, EN = 3V, TA = 25°C, ROUT = 200Ω. Maximum gain

specifications are with respect to differential inputs and differential outputs, unless otherwise noted.

(Note 7) (Test circuits shown in Figures 9 and 10)

AC ELECTRICAL CHARACTERISTICS

Note 1: Absolute Maximum Ratings are those values beyond which the life

of the device may be impaired.

Note 2: All voltage values are with respect to ground.

Note 3: Default state for open PGA inputs.

Note 4: VCC1 and VCC2 (Pins 2 and 19) are internally connected.

Note 5: External VOSUP is adjusted such that VCCO output pin common

mode voltage is as specified when resistors are used. For choke inductors

or transformer, VOSUP = VCCO = 5V typ.

Note 6: Internally generated common mode input bias voltage requires

capacitive or transformer coupling to the signal source.

Note 7: Specifications over the –40°C to 85°C operating temperature

range are assured by design, characterization and correlation with

statistical process controls. Gain always refers to power gain. Input

matching is assumed. PIN is the available input power. POUT is the power

into the external load, ROUT, as seen by the LT5524 differential outputs. All

dBm figures are with respect to 50Ω.

Note 8: High frequency operation is limited by the RC time constants at

the input and output ports. The low frequency (LF) roll-off is set by I/O

interface choice.

Note 9: Limited by package and board isolation.

Note 10: See “Clipping Free Operation” in the Applications Information

section. Refer to Figure 7.

Note 11: Although the instantaneous AC voltage on the OUT+ or OUT– pins

may in some situations safely exceed 8V (with respect to ground), in no

case should the DC voltage on these pins be allowed to exceed the

ABSMAX tested limit of 7V.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Dynamic Performance

BW

Large-Signal –3dB Bandwidth

All Gain Settings (Note 8), ROUT = 100Ω

LF to 540

MHz

VOUT(CLIP) Output Voltage Clipping Levels

Each OUT+, OUT– with Respect to Ground

2

8

V

(Note 11)

POUT(MAX) Clipping Limited Maximum Sinusoidal

All Gain Settings, Single Tone,

16

dBm

Output Power

fIN = 100MHz (Note 10)

gm

Amplifier Transconductance

Max Gain, fIN = 100MHz

0.15

S

S12

Reverse Isolation

fIN = 100MHz (Note 9)

–92

dB

Distortion and Noise

OIP3

Output Third Order Intercept Point for

POUT = 4dBm (Each Tone), 200kHz Tone Spacing,

PGA0 = High (PGA1, PGA2, PGA3 Any State)

fIN = 100MHz

+40

dBm

Output Third Order Intercept Point for

POUT = 4dBm (Each Tone), 200kHz Tone Spacing,

PGA0 = Low (PGA1, PGA2, PGA3 Any State)

fIN = 100MHz

+36

dBm

HD2

Second Harmonic Distortion

POUT = 5dBm (Single Tone), fIN = 50MHz

–76

dBc

HD3

Third Harmonic Distortion

POUT = 5dBm (Single Tone), fIN = 50MHz

–72

dBc

NFLOOR

Output Noise Floor

PGA1 = High, fIN = 100MHz

–138

dBm/Hz

(PGAO, PGA2, PGA3 Any State)

PGA1 = Low, fIN = 100MHz

–140

dBm/Hz

NF

Noise Figure

Max Gain Setting, fIN = 100MHz

8.6

dB

PGA Settling Time

Output Settles within 10% of Final Value

500

ns

Enable/Disable Time

Output Settles within 10% of Final Value

600

ns

Amplifier Power Gain and Gain Step

GMAX

Maximum Gain

fIN = 20MHz and 200MHz

27

dB

GMIN

Minimum Gain

fIN = 20MHz and 200MHz

4.5

dB

GSTEP

Gain Step Size

fIN = 20MHz and 200MHz

0.8

1.5

2.2

dB

Gain Step Accuracy

fIN = 20MHz and 200MHz

±0.2

dB

Amplifier I/O Impedance (Parallel Values, Specified Differentially)

RIN

Input Resistance

fIN = 100MHz

122

Ω

CIN

Input Capacitance

fIN = 100MHz

2

pF

RO

Output Resistance

fIN = 100MHz

5

kΩ

CO

Output Capacitance

fIN = 100MHz

1.7

pF

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