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A32200A-1PG256E Datasheet(PDF) 2 Page - Actel Corporation |
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A32200A-1PG256E Datasheet(HTML) 2 Page - Actel Corporation |
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2 / 98 page  2 H i g h -R e lia b i lity, L o w -R is k S o lu t i o n Actel builds the most reliable field programmable gate arrays (FPGAs) in the industry, with overall antifuse reliability ratings of less than 10 Failures-In-Time (FITs), corresponding to a useful life of more than 40 years. Actel FPGAs have been production proven, with more than five million devices shipped and more than one trillion antifuses manufactured. Actel devices are fully tested prior to shipment, with an outgoing defect level of less than 100 ppm. (Further reliability data is available in the Actel Device Reliability Report, at http://www.actel.com/hirel). Be ne f i t s Mi ni m i zed C o s t Ri s k With Actel’s line of development tools, designers can produce as many chips as they choose for just the cost of the device itself. There will be no NRE charges to cut into the development budget each time a new design is tried. Mi ni m i zed T i m e R i s k After the design is entered, placement and routing is automatic, and programming the device takes only about 5 to 15 minutes for an average design. Designers save time in the design entry process by using tools with which they are familiar. Mi ni m i zed R e l i abi l i ty R i s k The PLICE antifuse is a one-time programmable, nonvolatile connection. Since Actel devices are permanently programmed, no downloading from EPROM or SRAM storage is required. Inadvertent erasure is impossible, and there is no need to reload the program after power disruptions. Fabrication using a low-power CMOS process means cooler junction temperatures. Actel’s non-PLD architecture delivers lower dynamic operating current. Our reliability tests show a very low failure rate of 6.6 FITs at 90°C junction temperature with no degradation in AC performance. Special stress testing at wafer test eliminates infant mortalities prior to packaging. M i ni m i zed S ecu ri ty R i s k Reverse engineering of programmed Actel devices from optical or electrical data is extremely difficult. Programmed antifuses cannot be identified from a photograph or by using an SEM. The antifuse map cannot be deciphered either electrically or by microprobing. Each device has a silicon signature that identifies its origins, down to the wafer lot and fabrication facility. M i ni m i zed T e s ti ng Ri s k Unprogrammed Actel parts are extensively tested at the factory. Routing tracks, logic modules, and programming, debug and test circuits are 100 percent tested before shipment. AC performance is ensured by special speed path tests, and programming circuitry is verified on test antifuses. During the programming process, an algorithm is run to ensure that all antifuses are correctly programmed. In addition, Actel’s Silicon Explorer diagnostic tool uses ActionProbe circuitry, allowing 100 percent observability of all internal nodes to check and debug the design. Act e l F P GA D e s c r i pt i o n The Actel families of FPGAs offer a variety of packages, speed/performance characteristics, and processing levels for use in all high reliability and military applications. Devices are implemented in a silicon gate, two-level metal CMOS process, utilizing Actel’s PLICE antifuse technology. This P r o d u c t F a m ily P r o f ile Family ACT 2 ACT 1 Device A1240A A1280A A1010B A1020B Capacity System Gates Logic Gates SRAM Bits 6,000 4,000 NA 12,000 8,000 NA 1,800 1,200 NA 3,000 2,000 NA Logic Modules S-Modules C-Modules Decode 684 348 336 NA 1,232 624 608 NA 295 — 295 NA 547 — 547 NA Flip-Flops (maximum) 568 998 147 273 User I/Os (maximum) 104 140 57 69 Packages (by pin count) CPGA CQFP 132 — 176 172 84 — 84 84 Performance System Speed (maximum) 40 MHz 40 MHz 20 MHz 20 MHz |
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