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AGLP125-V2CSG289 Datasheet(PDF) 1 Page - Actel Corporation

Part # AGLP125-V2CSG289
Description  IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
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Manufacturer  ACTEL [Actel Corporation]
Direct Link  http://www.actel.com
Logo ACTEL - Actel Corporation

AGLP125-V2CSG289 Datasheet(HTML) 1 Page - Actel Corporation

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December 2008
I
© 2008 Actel Corporation
IGLOO PLUS Low-Power Flash FPGAs
with Flash*Freeze Technology
Features and Benefits
Low Power
• 1.2 V to 1.5 V Core Voltage Support for Low Power
• Supports Single-Voltage System Operation
• 5 µW Power Consumption in Flash*Freeze Mode
• Low-Power Active FPGA Operation
• Flash*Freeze
Technology
Enables
Ultra-Low
Power
Consumption while Maintaining FPGA Content
• Configurable Hold Previous State, Tristate, HIGH, or LOW
State per I/O in Flash*Freeze Mode
• Easy Entry To / Exit From Ultra-Low-Power Flash*Freeze Mode
Feature Rich
• 30 k to 125 k System Gates
• Up to 36 kbits of True Dual-Port SRAM
• Up to 212 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal, Flash-Based CMOS Process
• Live-at-Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design When Powered Off
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
•FlashLock® to Secure FPGA Contents
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
Advanced I/O
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—4 Banks per Chip on All
IGLOO® PLUS Devices
• Single-Ended
I/O
Standards:
LVTTL,
LVCMOS
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V
• Selectable Schmitt Trigger Inputs
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Small-Footprint Packages across the IGLOO
PLUS Family
Clock Conditioning Circuit (CCC) and PLL†
• Six CCC Blocks, One with an Integrated PLL
• Configurable
Phase
Shift,
Multiply/Divide,
Delay
Capabilities, and External Feedback
• Wide Input Frequency Range (1.5 MHz up to 250 MHz)
Embedded Memory
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)†
• True Dual-Port SRAM (except ×18)†
®
† The AGLP030 device does not support this feature.
Table 1-1 • IGLOO PLUS Product Family
IGLOO PLUS Devices
AGLP030
AGLP060
AGLP125
System Gates
30 k
60 k
125 k
Typical Equivalent Macrocells
256
512
1,024
VersaTiles (D-flip-flops)
792
1,584
3,120
Flash*Freeze Mode (typical, µW)
5
10
16
RAM kbits (1,024 bits)
–18
36
4,608-Bit Blocks
–4
8
Secure (AES) ISP
–Yes
Yes
FlashROM Bits
1 k1 k1 k
Integrated PLL in CCCs 1
1
1
VersaNet Globals 2
618
18
I/O Banks
44
4
Maximum User I/Os
120
157
212
Package Pins
CS
VQ
CS201, CS289
VQ128
CS201, CS289
VQ176
CS281, CS289
Notes:
1. AGLP060 in CS201 does not support the PLL.
2. Six chip (main) and twelve quadrant global networks are available for AGLP060 and AGLP125.
v1.3


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